Principal Engineer, SoC Architect

Ayar Labs; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Ayar Labs is looking for a Principal Engineer, SoC Architect in Bengaluru, India. The role focuses on defining next-generation SoC architectures for high-performance semiconductor products and requires deep expertise in system-level architecture and high-speed I/O integration.

The ideal candidate will collaborate across multiple teams to drive innovation in SoC platforms, ensuring robust solutions with a strong emphasis on performance optimization and scalability.

Qualifications

• 12+ years of experience in SoC/system architecture and semiconductor product development.
• Proven expertise in large-scale SoC architecture definition.
• Experience with architecture modeling tools and performance analysis.

Responsibilities

• Define end-to-end SoC architecture for complex semiconductor platforms.
• Drive architectural tradeoff analysis involving performance, power, area, and cost.
• Develop architectural specifications and collaborate across teams.

Skills

High-speed I/O integration

System-level architecture

Performance optimization

Technical leadership

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering

Tools

Architecture modeling tools

Job description

Position

Principal Engineer, SoC Architect

Location

Bengaluru, India

Job Id

633

# of Openings

0

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.

Role Overview

We are seeking a highly experienced Principal Engineer – SoC Architect to define and drive next‑generation SoC architectures for high‑performance semiconductor products. This role requires deep expertise in system‑level architecture, high‑speed I/O integration, performance optimization, scalability, and cross‑functional technical leadership. The ideal candidate will play a critical role in shaping SoC platforms from concept through silicon realization, with strong emphasis on high‑speed interfaces, subsystem architecture, interoperability, power/performance optimization, and architectural innovation.

Key Responsibilities

• Define end-to-end SoC architecture for complex semiconductor platforms across compute, memory, interconnect, security, and peripheral subsystems.
• Drive architectural tradeoff analysis involving performance, power, area (PPA), latency, scalability, and cost.
• Develop architectural specifications, subsystem partitioning, and top‑level integration strategies.
• Collaborate with product, software, firmware, RTL, verification, physical design, and validation teams throughout the development lifecycle.
• Lead architecture and integration of high‑speed interfaces including: PCIe, Ethernet, USB, SerDes, CXL/UCIe and other advanced interconnect protocols.
• Define bandwidth, latency, coherency, buffering, QoS, and interoperability requirements.
• Drive system‑level performance modeling and interface optimization.
• Partner with PHY, signal integrity, packaging, and board teams to ensure robust end‑to‑end solutions.

System Performance & Modeling

• Develop architectural models, traffic analysis, and workload characterization frameworks.
• Drive power‑aware architecture decisions and dynamic performance management strategies.

Technical Leadership

• Provide architectural leadership across multiple SoC programs and product generations.
• Mentor senior engineers and influence organization‑wide architectural methodologies.
• Lead technical reviews, design evaluations, and architecture signoff discussions.
• Drive alignment across hardware, firmware, software, and platform ecosystems.

Cross‑Functional Collaboration

• Work closely with Design and verification teams on implementation feasibility, Firmware/software teams on boot, drivers, and runtime optimization, Validation teams on bring‑up and debug strategies and Product and business teams on roadmap alignment.
• Interface with external IP vendors and ecosystem partners when required.

Required Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in SoC/system architecture and semiconductor product development.
• Proven expertise in large‑scale SoC architecture definition and subsystem integration.
• Strong understanding of high‑speed I/O architectures and protocols, on‑chip interconnects and coherency fabrics, memory subsystem architecture, performance modeling and analysis and power/performance optimization techniques.
• Experience with architecture modeling tools, simulation environments, and performance analysis methodologies.
• Strong technical communication and leadership skills.

Preferred Qualifications

• Deep expertise in one or more high‑speed I/O technologies such as PCIe Gen5/Gen6, CXL, UCIe, HBM, or advanced SerDes architectures.
• Experience with heterogeneous compute architectures involving CPU, GPU, AI/ML accelerators, or DSP subsystems.
• Knowledge of chiplet‑based architectures and advanced packaging technologies.
• Experience with silicon bring‑up, post‑silicon debug, and system validation.
• Familiarity with automotive, AI/ML, datacenter, networking, or mobile SoC platforms.
• Publications, patents, or industry contributions in SoC or high‑speed interconnect architecture are a plus.
• Influence long‑term SoC technology and platform strategy.
• Drive innovation in scalable and reusable architecture frameworks.
• Champion engineering excellence, design quality, and execution rigor.
• Foster collaboration across globally distributed engineering organizations.