verification Engineer _2831

Sunrise Biztech Systems; Hyderabad; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Sunrise Biztech Systems in Hyderabad is seeking a Verification Engineer to participate in functional verification of ASICs and IP cores. You will work with a team to verify complex CPU/GPU development efforts and document test plans with directed and constrained-random tests during simulation.

The role requires 3–6 years in verification, strong C/C++ skills on Linux, and knowledge of Verilog/SystemVerilog; familiarity with DPI/PLI is a plus. Immediate joiners preferred.

Qualifications

• 2–4 years verification on ASIC projects or hardware development
• Strong background in C/C++ development in Linux environment
• Experience with Verilog/SystemVerilog/SystemC; DPI/PLI preferred
• Proficient in OO programming, STL, data structures
• Perl and Makefiles knowledge

Responsibilities

• Participate in functional verification of ASICs and IP cores within CPU/GPU development
• Work with a team of design and verification engineers to verify design elements
• Document and execute test plans with directed and constrained-random tests in simulation
• Adopt evolving verification methodologies to verify increasingly complex SoC designs
• Familiarity with hardware modelling and assertion-based verification methods

Skills

C

C++

SystemVerilog

Education

2-4 years proven verification experience on large ASIC projects

Tools

Verdi

VCS

GDB

Valgrind

Job description

Position: Verification Engineer Experience: 3-6 Years

Location: Hyderabad

Full Time Employment/Contractual

Top 3 skills:

• Have Excellent debugging skills, Knowledge of C, C++, System verilog, Need to have hands on debug tools like verdi, vcs.Coverage knowledge, graphics Knowledge

Role & responsibilities:

• Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
• Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
• Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
• Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

• 2-4 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
• Strong background in C/C++ development in a Linux Environment;Strong debug skills and experience with debug tools such as Gdb, Valgrind;
• Proficient in Object Oriented programming, STL, computer architecture and data structures;
• Knowledge of Perl and Makefiles;
• Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;
• Strong analytical skills and attention to detail;Excellent written and communication skills

Preferred candidate profile :

Immediate joiners or 15 days/30days Np candidates preferred