Timing Constraint Development Engineer

Advanced Micro Devices, Inc.; Hyderabad; Sur place; INR 1 200 000 - 2 200 000; Plein temps

Résumé du poste

Advanced Micro Devices, Inc. is seeking a Timing Constraint Development Engineer to own SDC development for IPs, subsystems and SoCs. This role involves planning, generation, verification and promotion of constraints, with potential expansion to synthesis and post-layout timing closure.

Collaboration with design and PNR teams is essential to meet schedules. The ideal candidate will have strong experience in SDC, RTL/Netlist checks, and top-level or SOC-level designs, along with a passion for AI,

Qualifications

• Bachelor's with 7 years of experience or Master's with 5 years in Electrical Engineering.
• Experience with SDC development and timing constraints for IPs/SS/SoCs.
• Synthesis, LEC, CLP and timing closure experience is preferred.
• Top-level or SOC-level experience is desirable.
• Understanding of timing constraints, low power and DFT concepts.
• Debug experience to resolve issues and automation interest.

Responsabilités

• Own constraints and SDC development for IPs, SS and SoCs, including generation, verification, and promotion/demotion.
• Work with design and PNR teams to achieve timing closure.
• Plan and execute timing activities within schedule and ensure quality delivery.
• Support synthesis and timing closure through debugging and issue resolution.

Connaissances

Timing constraints

SDC development

RTL & Netlist static checks

Formation

Electrical Engineering (Bachelors or Masters)

Outils

Fisthail

Excellicon

TCM

Description du poste

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

MTS Timing constraint development ENGINEER

THE ROLE:

The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:

• Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
• Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
• Collaborate with designer and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.
• Complete quality delivery for synthesis and timing closure.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:

• Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
• Experienced in synthesis, LEC, CLP and timing closure
• Preferred top level or SOC level experience
• Have handled blocks with complex designs, high frequency clocks and complex clocking
• complete understanding of timing constraints, low power aspects and concepts of DFT
• Have debug experience to solve issues.
• Interst in AI, Scripting and automation

ACADEMIC CREDENTIALS:

• Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.