DFT Timing Lead

AMD; Bengaluru Urban; Hybrid; INR 2,500,000 - 4,500,000; Full time

Benefits offered by this job

Hybrid work

Job summary

AMD in Bengaluru is seeking an experienced SMTS/MTS Silicon Design Engineer to drive DFT for next-gen SoCs, focusing on structural DFT, ATPG, MBIST and DFT constraints.

The role collaborates with Design and Physical teams to finalize timing constraints and automate DFT processes; requires 8–15 years in DFT and RTL quality tools.

Qualifications

• Experience in DFT architecture for complex chips.
• Exposure to Static timing analysis & Timing closure is required.
• Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).
• Experience in SOC timing closure in DFT modes and sign-off.
• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
• Excellent hands-on debug skills and scripting skills are critical.

Responsibilities

• Develop full chip DFT Synthesis and DFT STA constraints.
• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)
• Set up DFT timing constraints, defining the overall SOC Test STA methodology.
• Working with the Design team to clean-up all the DFT related constraint issues
• Closely work with physical design team to generate and validate timing constraints
• Developing, improving and maintaining automation scripts as necessary

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

SMTS/MTS Silicon Design Engineer

The Role:

• As a key member of the S3 SoC DFT Team, the successful candidate will play a significant role in ensuring the quality of next generation AMD SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.

Key Responsibilities:

• Develop full chip DFT Synthesis and DFT STA constraints.
• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)
• Set up DFT timing constraints, defining the overall SOC Test STA methodology.
• Working with the Design team to clean-up all the DFT related constraint issues
• Closely work with physical design team to generate and validate timing constraints
• Developing, improving and maintaining automation scripts as necessary

Preferred Experience:

• Experience in DFT architecture for complex chips
• Exposure to Static timing analysis & Timing closure is required.
• Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).
• Experience in SOC timing closure in DFT modes and sign-off
• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.
• Excellent hands-on debug skills and scripting skills are critical.

Qualification:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT Experience

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Benefits offered are described: AMD benefits at a glance

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.