DFT Timing Lead

Advanced Micro Devices, Inc.; Bengaluru; Hybrid; INR 2,600,000 - 5,600,000; Full time

Job summary

AMD in Bengaluru invites an experienced SMTS/MTS Silicon Design Engineer to contribute to DFT and STA, collaborating with Design and Physical teams. You will set up timing constraints and SOC test methodologies for complex chips, while enhancing automation scripts and debugging RTL paths.

Ideal candidates have DFT architecture experience, STA expertise, and familiarity with SpyGlass, CDC and Lint. This hybrid role offers growth in a leading semiconductor environment.

Qualifications

• BE/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT experience.
• Experience with DFT constraints and SOC timing in ASICs.
• Strong debugging and scripting abilities.
• Knowledge of STA tools and RTL quality checks.

Responsibilities

• Develop full chip DFT Synthesis and DFT STA constraints.
• Develop STA constraints for DFT modes (ScanShift, Atspeed, MBIST).
• Set up DFT timing constraints and SOC test STA methodology.
• Collaborate with Design and Physical teams to resolve DFT constraint issues.
• Create, improve, and maintain automation scripts.
• Support DFT validation and sign-off during tape-out.

Skills

DFT architecture

Static timing analysis

Timing closure

RTL debugging

Scripting

Education

BE/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

Tools

SpyGlass

CDC

Lint

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

SMTS/MTS Silicon Design Engineer

The Role:

Key Responsibilities:

• Develop full chip DFT Synthesis and DFT STA constraints.


• STA constraint development of DFT modes (ScanShift, Atspeed, MBIST)


• Set up DFT timing constraints, defining the overall SOC Test STA methodology.


• Working with the Design team to clean-up all the DFT related constraint issues


• Closely work with physical design team to generate and validate timing constraints


• Developing, improving and maintaining automation scripts as necessary

Preferred Experience:

• Experience in DFT architecture for complex chips


• Exposure to Static timing analysis & Timing closure is required.


• Proven experience in DFT constraints handling, Block and Top-level test mode Static timing analysis (STA).


• Experience in SOC timing closure in DFT modes and sign-off


• Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required.


• Excellent hands‑on debug skills and scripting skills are critical.

Qualification:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering with 8 to 15 years of DFT Experience

#LI-RR1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.