Senior STA Design Engineer

AMD; Bengaluru Urban; Vor Ort; INR 2.800.000 - 4.200.000; Vollzeit

Benefits dieser Stelle

AMD benefits

Zusammenfassung

AMD in Bengaluru seeks a Senior STA Silicon Design Engineer to own complex timing constraints for IPs, blocks and full chips. You will drive timing closure, ensure SDC quality, and collaborate with RTL teams to deliver high-frequency, reliable silicon.

The role requires 4-5 years of hands-on experience, strong TCL scripting, and proficiency with industry tools such as Primetime, Design Compiler, Spyglass, Fishtail and Tweaker. AMD offers competitive benefits and a dynamic environment.

Qualifikationen

• Bachelors or Masters in Computer Engineering or Electrical Engineering.
• Experience building timing constraints for IPs, blocks and full-chip implementations.
• Strong TCL/scripting proficiency and hands-on EDA tool usage.

Aufgaben

• Develop complex multi-mode / multi-corner timing constraints for RTL and signoff.
• Ensure constraints quality (SDC) using industry tools.
• Lead pre-route timing checks and QoR cleanup to enable STA signoff.
• Drive timing closure for sub-chip, subsystem or full-chip.
• Generate timing ECOs using DMSA/Tweaker.

Kenntnisse

Timing constraints

SDC

Tcl scripting

Timing closure

DFT timing

Ausbildung

Bachelors or Masters in Computer/Electrical Engineering

Tools

Synopsys Design Compiler

Primetime

Spyglass

Fishtail

Tweaker

Jobbeschreibung

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

SENIOR STA SILICON DESIGN ENGINEER

KEY RESPONSIBILITIES:

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff


• Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA


• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks

• Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)


• Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.


• Ensuring Subsystem/full chip level Interface timing closure along DRV closure


• Generating timing ECO using tools DMSA/Tweaker.

PREFERRED EXPERIENCE:

• 4-5 years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.


• Experience with analyzing the timing reports and identifying both the design and constraints related issues.


• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.

• Experience in timing closure of high frequency blocks & subsystems (> Ghz range )

• Good Understanding of DFT modes requirements for timing signoff


• Good understanding of SDC constraints, OCV,AOCV,POCV analysis.


• Strong TCL/scripting knowledge is mandatory.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering

#LI-SR4

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.