Timing Constraint Development Engineer

AMD; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD Hyderabad, India is seeking an MTS Timing constraint development engineer to own SDC development for IPs, SS and SoCs. You will coordinate with design and PNR teams to ensure timing closure and quality delivery across synthesis flows.

The role emphasizes planning, verification, and promotion/demotion of SDC, with familiarity in Lint, CDC, RTL/Netlist checks and complex clocking scenarios.

Qualifications

• Experience with timing constraints development for IPs/SS/SoCs.
• Familiar with Lint, CDC and RTL/Netlist static checks.
• Collaborate with design and PNR teams to achieve timing closure.

Responsibilities

• Own constraints and SDC development for IPs, SS and SoCs.
• Develop, verify, promote/demote SDC and ensure equivalence.
• Coordinate with design and PNR teams to achieve closure.
• Plan and execute as per schedule with quality delivery for synthesis and timing closure.
• Debug and resolve technical issues.

Skills

Timing constraints

SDC development

Scripting & automation

Lint/CDC/RTL checks

Synthesis/LEC/CLP

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Fisthail

Excellicon

TCM

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whetheryou're redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.

MTS Timing constraint development ENGINEER

THE ROLE:

The focus of this role is to plan and develop the Timing constraints of IPs Subsystem or Full chip. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also expand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:

• Main responsibility is to own constraints, SDC development for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools.
• Prior experience with Lint, CDC and RTL & Netlist based static checks is a plus
• Collaborate with designer and PNR teams to achieve closure.
• Understand duration required, plan and execute as per schedule.
• Complete quality delivery for synthesis and timing closure.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:

• Existing SDC, constraints development with or without using fisthail, excellicon or TCM.
• Experienced in synthesis, LEC, CLP and timing closure
• Preferred top level or SOC level experience
• Have handled blocks with complex designs, high frequency clocks and complex clocking
• complete understanding of timing constraints, low power aspects and concepts of DFT
• Have debug experience to solve issues.
• Interst in AI, Scripting and automation

ACADEMIC CREDENTIALS:

• Bachelors with 7 years of experience or Masters degree with 5 years of experience in Electrical Engineering

#LI-AB1

Benefits offered is described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.