Lead Full-chip STA and timing signoff Engineer

AMD; Bengaluru Urban; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

AMD in Bengaluru seeks an experienced Full Chip SoC Timing Lead to guide timing closure from synthesis through tapeout for complex SoCs in advanced nodes. The role requires deep expertise in STA, timing constraints, MMMC, SI/crosstalk, ECO closure, and cross-functional collaboration with RTL, PD, CTS, DFT, power, and signoff teams.

You will mentor engineers, drive timing strategies, and collaborate across teams to ensure robust, on-time delivery while optimizing power and area.

Qualifications

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering.
• 12+ years hands-on experience in ASIC/SoC timing analysis and timing closure.
• Strong expertise in full-chip STA and timing signoff for large-scale SoCs.
• Proven experience in advanced technology nodes (7nm, 5nm, 3nm or similar).
• Strong knowledge of synthesis, place-and-route, extraction, and signoff flows.
• Ability to debug complex timing issues and drive closure under aggressive schedule targets.
• Excellent communication, stakeholder management, and leadership skills.

Responsibilities

• Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners.
• Own and drive timing signoff from synthesis to final tapeout.
• Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration.
• Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths.
• Drive MMMC timing methodology and ensure robust timing convergence across PVT corners.
• Collaborate with RTL/PD/CTS/DFT/power/signoff teams on timing-related issues.
• Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, and variations.
• Lead timing ECO strategies and execute closure with minimal impact on power, area, and performance.
• Coordinate with IP/block owners for timing budgeting and hierarchical timing signoff.
• Ensure signoff quality using industry-standard tools and methodologies.
• Lead tapeout readiness reviews and provide timing risk assessment to program leadership.
• Mentor junior engineers and define best practices for timing methodology.

Skills

Full-chip timing

STA

Timing constraints

MMMC flows

Signoff ownership

Synthesis to tapeout

Cross-functional collaboration

Leadership

Mentoring

RTL collaboration

Education

Electronics/Electrical/VLSI degree

Tools

Synthesis

Place-and-route

Signoff tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

We are seeking an experiencedFull Chip SoC Timing Lead inASIC/SoC design implementation and timing closure. The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This role requires deep expertise inSTA, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaborationwith RTL, PD, CTS, DFT, power, and signoff teams.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Leadfull-chip timing closurefor complex SoC/ASIC designs across all modes and corners.


• Own and drivetiming signofffrom synthesis to final tapeout.


• Develop, validate, and maintaintiming constraintsincluding SDC for full-chip and block-level integration.


• Perform and reviewstatic timing analysis (STA)for setup, hold, recovery, removal, clock gating, and async paths.


• DriveMMMC timing methodologyand ensure robust timing convergence across PVT corners.


• Work closely withphysical design teamson floorplanning, placement, CTS, routing, and post-route timing optimization.


• Analyze and resolvetiming violationsrelated to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects.


• Leadtiming ECO strategiesand execute closure with minimal impact to power, area, and performance.


• Collaborate withRTL/design teamsto identify architectural or logic changes required for timing improvement.


• Coordinate withIP/block ownersfor timing budgeting, interface timing closure, and hierarchical timing signoff.


• Ensure signoff quality using industry-standard tools and methodologies.


• Drive correlation betweenimplementation timingandsignoff timing.


• Lead tapeout readiness reviews and provide timing risk assessment to program leadership.


• Mentor junior engineers and define best practices for timing methodology and closure.

PREFERRED EXPERIENCE:

• Bachelor’s or Master’s degree inElectronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering.


• 12+ yearsof hands-on experience inASIC/SoC timing analysis and timing closure.


• Strong expertise infull-chip STA and timing signofffor large-scale SoCs.


• Proven experience inadvanced technology nodes(such as7nm, 5nm, 3nmor similar).


• Strong knowledge ofsynthesis, place-and-route, extraction, and signoff flows.


• Experience withtiming budgeting and hierarchical/full-chip integration.


• Solid understanding ofclocking architecture, CDC implications, and timing exception handling.


• Ability to debug complex timing issues and drive closure under aggressive schedule targets.


• Strong communication, stakeholder management, and leadership skills.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.