Lead Engineer - Silicon Networking (ASIC Design & Development)

Google India Pvt Ltd; Bengaluru; Presencial; INR 6 000 000 - 9 000 000; Tempo integral

Resumo da oferta

Google India Pvt Ltd in Bengaluru is seeking a Silicon Networking Lead to drive ASIC development from design to tape-out. You will work with architecture, software, verification, power, timing, synthesis, and other teams to deliver high-quality SoC/RTL and IPs.

The role requires guiding a multi-disciplinary team, strong experience in architecture, RTL, and silicon bring-up, and delivering optimized performance and power.

Qualificações

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 15 years of experience in ASIC design and development.
• Experience leading multi-disciplinary silicon engineering teams through the full development life-cycle from architecture definition to tape-out.
• Experience in high-performance or low-power design techniques, ASIC standard interfaces, and memory system architectures.

Responsabilidades

• Own the Silicon Networking organization in Bengaluru, including definition, implementation and deployment of Networking IPs.
• Define IP development methodologies and drive deep technical involvement across the IP's development cycle, including seamless integration to SoC.
• Lead project planning from architecture and micro-architecture decisions to scoping effort, collaborating across teams to represent project status.
• Lead and manage a multi-disciplinary team of chip engineers, plan tasks, allocate people, and hold technical design/code reviews.
• Guide and participate across the entire ASIC lifecycle, spanning architecture definition, RTL development, synthesis, timing/power, FPGA/silicon bring-up, and verification strategy.
• Drive the full development life-cycle of chips from initial definition to a high-quality tape-out.
• Ensure developed IPs contribute effectively across multiple key projects.
• Collaborate closely with cross-functional teams and other sites around the globe.

Conhecimentos

ASIC design

Silicon leadership

SoC RTL

high-performance design

memory system architectures

architecture definition

cross-functional collaboration

Formação académica

Bachelor's degree or equivalent in Electrical/Computer Engineering or CS

Ferramentas

FPGA

Emulation platforms

SOC architecture

Descrição da oferta de emprego

Silicon Networking Lead, Google Cloud

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience in ASIC design and development.
• Experience leading multi-disciplinary silicon engineering teams through the full development life-cycle from architecture definition to tape-out.
• Experience in high-performance or low-power design techniques, ASIC standard interfaces, and memory system architectures.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ASIC standard interfaces and memory system architecture.
• Knowledge of high-performance and low power design techniques.
• Knowledge of FPGA, emulation platforms, and SOC architecture.
• Knowledge of one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will serve as the overall Silicon Networking Lead for our Bengaluru organization. You will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver high quality SoC/RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will serve as the overall Silicon Networking Lead for our Bengaluru organization. You will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver high quality SoC/RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Responsibilities

Own the Silicon Networking organization in Bengaluru, including definition, implementation and deployment of Networking IPs. Define IP development methodologies and drive deep technical involvement across the IP's development cycle, including seamless integration to SoC. Lead project planning from architecture and micro-architecture decisions to scoping effort, collaborating across teams to represent project status. Lead and manage a multi-disciplinary team of chip engineers, plan tasks, allocate people, and hold technical design/code reviews. Guide and participate across the entire ASIC lifecycle, spanning architecture definition, RTL development, synthesis, timing/power, FPGA/silicon bring-up, and verification strategy. Drive the full development life-cycle of chips from initial definition to a high-quality tape-out. Ensure developed IPs contribute effectively across multiple key projects. Collaborate closely with cross-functional teams and other sites around the globe.

Experience Level Senior Level