System Modelling Engineer

Intel; Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Intel is seeking an experienced Analog and Mixed Signal IP Architect to lead the architecture, modeling, and analysis of 224Gbps SerDes IP. This role will focus on developing innovative architectures and algorithms for next-gen analog and mixed signal IPs.

Candidates should possess a Bachelor's degree in Electrical Engineering (12+ years experience) or a Master's/PhD (8+/4+ years respectively). Key responsibilities include modeling electrical channels and leading compliance with industry standards.

Qualifications

• 12+ years of relevant experience is required for Bachelor's degree holders.
• Ability to model, simulate, and optimize performance for analog and mixed signal IPs.
• Experience with TX/RX blocks and system-level understanding.

Responsibilities

• Develop end-to-end behavioral models for 224Gbps SerDes PHYs.
• Model electrical channels and develop equalization algorithms.
• Analyze PLL/DLL behavior, phase noise, and jitter.

Skills

Proficiency in analog circuit design

Expertise in architecture modeling

Strong analytical skills

Effective communication skills

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree and 8+ years of experience

PhD and 4+ years of experience

Job description

Job Details

As an Analog and Mixed Signal IP Architect, you will play a pivotal role in shaping the future of Intel's cutting‑edge technologies. You will be responsible for driving innovative architectures and algorithms that define the next generation of System‑on‑Chip (SoC) independent analog and mixed signal IPs. We are seeking an experienced SerDes PHY System Modeling Engineer to lead and support the architecture, modeling, and performance analysis of 224Gbps SerDes IP. The role focuses on end‑to‑end PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis, enabling robust silicon implementation for next‑generation ASICs and SoCs.

Key Responsibilities

System Architecture and Modeling: Develop end‑to‑end behavioral models for 224Gbps SerDes PHYs across TX, channel, and RX. Build statistical and timedomain system models to evaluate BER, eye margins, and link robustness. Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss). Model and optimize PAM4 signaling at very high data rates.

Channel and Equalization Analysis: Model electrical channels, including packages, PCBs, connectors, and crosstalk. Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms. Perform swept channel analysis to ensure compliance across worst‑case conditions. Support co‑optimization of channel, package, and PHY architecture.

Clocking, Jitter and Noise Analysis: Model PLL/DLL behavior, phase noise, and jitter transfer functions. Perform jitter decomposition (RJ, DJ, PJ, SJ) and bathtub curve analysis. Analyze CDR performance, loop dynamics, and tolerance to jitter/noise sources.

Compliance and Standards Support: Support modeling and interpretation of industry standards (IEEE, OIF, etc.), including 224G related efforts. Define channel and compliance test methodologies. Align system models with compliance test specifications and silicon validation strategies. Work closely with circuit designers, DSP/algorithm teams, package/PCB engineers, and validation teams. Translate system‑level requirements into block‑level and circuit‑level specs. Support silicon bring‑up and debug through correlation of lab data with system models.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field, and 12+ years of relevant experience; or Master's degree and 8+ years of relevant experience; or PhD and 4+ years of relevant experience.
• Proficiency in analog circuit design, including TX/RX blocks and system‑level understanding.
• Expertise in architecture modeling and high‑speed design techniques.
• Demonstrated ability to model, simulate, and optimize performance, power, and area for analog and mixed signal IPs.

Preferred Qualifications

• Strong leadership and collaboration skills with experience in influencing cross‑functional technology roadmaps.
• Solid analytical and problem‑solving abilities with a track record of delivering innovative solutions.
• Effective communication skills to articulate architectural features and trade‑offs to design teams and stakeholders.
• A passion for advancing technology and contributing to Intel's mission of innovation and excellence.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.