Mixed Signal IP Verification Engineer

Intel; Bengaluru; Hybrid; INR 4,200,000 - 6,200,000; Full time

Job summary

Intel in Bangalore seeks a Pre-Silicon Verification Engineer to deliver DDR PHY IP across Intel platforms. You will drive the full functional verification flow, create test plans, define testbench architecture, and build test benches to validate design and micro-architectural implementations.

You will automate validation, analyze results, debug issues pre-silicon, and collaborate with RTL, analog, and physical design teams to meet functional, performance and power goals while contributing to

Qualifications

• BS or MS degree with 5–10 years of experience in design verification, SystemVerilog, and OVM/UVM.
• Experience in validation flow from testbench architecture to verification closure, waveform debug, and coverage.
• Ability to multitask in a dynamic environment with multiple geos.
• Strong verbal and written communication skills.
• Excellent debugging and problem-solving abilities.

Responsibilities

• Perform all aspects of the functional verification flow to ensure design meets specifications.
• Create test plans and define testbench architecture and benches.
• Validate design and micro-architectural implementation across IP, subsystems, and SoC levels.
• Automate validation tasks to drive efficiency and analyze results.
• Collaborate with RTL, analog, and physical design teams to meet goals.
• Maintain and improve verification infrastructure and methodology.

Skills

Design verification

SystemVerilog

OVM/UVM

Communication

Debug & problem-solving

Multitasking

Education

BS/MS in a relevant field

Tools

Git

GitHub

VSCode

Copilot

Python

Job description

Job Details

The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for a Pre-Silicon Verification Engineer to deliver the latest and best‑in‑class DDR PHY IP for SoCs across Intel for the latest desktop, laptop, and other products. In this role you will perform all aspects of the functional verification flow to ensure the design meets specification requirements. You will perform IP Verification related tasks such as creating the test plan, defining the testbench architecture and creating test benches, validating design and micro‑architectural implementation. You will automate validation tasks to drive efficiency, analyze results, and help debug issues in the pre‑silicon environment at IP, subsystem, and SoC levels. You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and micro‑architectural features and to meet functional, performance, and power goals. Additional responsibilities include: developing validation strategies and plans, scoping and driving execution for different areas of pre‑Si validation, driving technical reviews of plans and proofs with design and architecture teams, maintaining and improving existing functional verification infrastructure and methodology, providing guidance and help to team members in understanding issues, removing roadblocks, and ensuring issue resolution through a strong demonstration of Intel cultural values.

Qualifications

Minimum Qualifications:

• Candidate must possess a BS or MS degree with 5‑10 years of relevant industry experience in Design verification, System Verilog, and OVM/UVM.
• Candidate must be experienced in the validation flow from testbench architecture and test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non‑NLP simulations, and GLS.
• Capable of multitasking in a dynamic environment with multiple teams from different geos.
• Solid verbal and written communication skills.
• Excellent debug and problem‑solving skills.

Preferred Qualifications:

• Knowledge of DDRPHY validation with a good understanding of DFx features.
• Good scripting skills in Python or Perl.
• Exposure to Git version control, VSCode, GitHub, Copilot, or any other AI experience.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Business Group

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location, or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.