Analog Circuit Design Engineer

Intel; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Intel is seeking an Analog Circuit Design Engineer in Bengaluru, India, to advance analog and mixed-signal designs for high-speed solutions. The ideal candidate will have extensive experience in analog circuit design, particularly for high-speed SerDes systems.

Responsibilities include designing and optimizing analog circuits, working closely with cross-functional teams, and contributing to the validation and debugging of silicon designs.

Applicants should hold a relevant Bachelor's degree and possess strong analytical skills.

Qualifications

• 14+ years of experience with a Bachelor's degree, 12+ years with a Master's, or 8+ years with a Ph.D.
• Expertise in analog circuit design for high-speed SerDes.
• Strong fundamentals in CMOS design and circuit concepts.

Responsibilities

• Design and optimize high-speed SerDes PHY analog blocks.
• Perform transistor-level design, simulation, and optimization.
• Define and execute post-silicon validation plans.

Skills

Analog circuit design

High-speed SerDes

Silicon validation

Signal integrity

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Virtuoso

MATLAB

Job description

Job Details

Job Description: Join Intel's cutting-edge team as an Analog Circuit Design Engineer, where you will play a pivotal role in advancing analog and mixed‑signal designs for high‑speed interconnect solutions. You will design and verify analog circuits in advanced process nodes, contributing directly to Intel's next‑generation innovations. Collaborating with cross‑functional teams, you will optimize circuits for power, performance, area, timing, and yield goals while driving impactful solutions that shape Intel's leadership in technology.

Key Responsibilities

• Design and optimize high‑speed SerDes PHY analog blocks for 224G/112G SerDes.
• Have silicon‑proven hands‑on design experience with Clock and Data Recovery circuits, Phase Interpolators, DLL, high‑speed TX drivers, and RX front‑end circuits.
• Architect low‑jitter, low‑power, and high‑linearity circuits meeting stringent BER and jitter specifications.
• Perform transistor‑level design, simulation, and optimization for PVT corners, aging, mismatch, and reliability.
• Work closely with SerDes architects to translate system‑level requirements (channel loss, BER, jitter tolerance, power, latency) into circuit‑level specifications.
• Support link‑level modeling and behavioral abstraction of analog blocks for top‑level system simulations.
• Contribute to architecture trade‑offs between performance, power, area, and testability.
• Drive pre‑silicon verification using Spectre/HSPICE, AMS simulations, and MATLAB/Python modeling.
• Define and execute post‑silicon validation plans, including debug, characterization, and bring‑up in the lab.
• Analyze silicon data and correlate with simulations; propose and implement ECOs as needed.
• Support compliance testing with standards such as IEEE 802.3 (112G/224G) and industry interoperability requirements.
• Interface with digital, firmware, packaging, SI/PI, and test engineering teams.
• Participate in design reviews, risk assessments, and schedule planning.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 14+ years of experience with a Bachelor's degree, 12+ years with a Master's degree, or 8+ years with a Ph.D.
• Expertise in analog circuit design for high‑speed SerDes, transmitter, receiver, clocking, PLL, and DLL.
• Strong fundamentals in CMOS design, RC circuits, high‑speed circuit concepts, and signal integrity.
• Proficiency in analog design tools such as Cadence Virtuoso/ADE or equivalent.
• Demonstrated experience in post‑silicon validation and debugging.
• Knowledge of advanced FinFET CMOS process technologies.
• Excellent analytical and problem‑solving skills.

Preferred Qualifications

• Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline.
• Hands‑on experience with modeling and simulation of high‑speed channels and interconnects.
• Familiarity with high‑speed communication standards such as PCIe, Ethernet, and next‑generation protocols.
• Experience with Verilog‑A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl).
• Demonstrated ability to mentor junior engineers and foster a collaborative team environment.
• Strong communication skills, both written and verbal, to effectively influence stakeholders and drive technical decisions.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Work Model

This role will require an on‑site presence.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.