Mixed Signal Logic Design Engineer

Intel; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Intel in Bengaluru is seeking a Mixed Signal Logic Design Engineer to contribute to high-speed, low-power IPs for next-generation products. You will own RTL design and work with cross-functional teams to deliver robust IP blocks.

The role emphasizes power and performance optimization, automation flows for design verification, and collaboration with SoC teams to ensure seamless integration and timely delivery.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or closely related field.
• 4–12 years experience with a Bachelor's or 3–10 years with a Master's.
• Strong expertise in RTL development using SystemVerilog.
• Proficiency in low-power design techniques including UPF, clock gating, and multiple clock domain design.
• Hands-on experience with front-end design tools such as Spyglass, VC Lint, CDC, and synthesis tools.
• Solid understanding of state machine design, simulation, and debugging using VCS and Verdi.
• Scripting proficiency in Perl, Python, or TCL for design automation and workflow optimization.

Responsibilities

• Define and implement microarchitecture and RTL designs for mixed-signal and high-speed IP blocks using SystemVerilog.
• Collaborate with architecture and system teams to optimize power, performance, and area for IP designs.
• Develop and utilize automation flows for IP logic design, ensuring high-quality RTL through tools like Lint, CDC, and synthesis QA checks.
• Conduct power and performance analysis, driving improvements in area and power efficiency across designs.
• Review verification plans and resolve RTL issues to ensure feature correctness and design integrity.
• Support SoC teams, ensuring seamless integration and high-quality delivery of IP modules.
• Innovate and implement automated solutions to streamline coverage closure and timing convergence.

Skills

SystemVerilog RTL

UPF clock-gating

Multiple clock domains

Scripting: Perl/Python/TCL

RTL debugging

Education

Bachelor's in Electrical or Computer Engineering

Master's in Electrical or Computer Engineering

Tools

Spyglass

VC Lint

CDC

Synthesis tools

VCS

Verdi

Job description

Job Description

The Role and Impact As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of industry‑leading technologies by contributing to the development of high‑speed, low‑power IPs for next‑generation products. You will work in a dynamic, innovative environment, collaborating with cross‑functional teams to deliver robust and efficient mixed‑signal designs. By owning and delivering the logic design of Mixed Signal IPs, you will directly influence Intel's mission to create world‑changing technology that enables global progress and enriches lives.

Key Responsibilities

• Define and implement microarchitecture and RTL designs for mixed signal and high‑speed IP blocks using System Verilog.
• Collaborate closely with architecture and system teams to optimize power, performance, and area for IP designs.
• Develop and utilize automation flows for IP logic design, ensuring high‑quality RTL through tools such as Lint, CDC, and synthesis QA checks.
• Conduct power and performance analysis, driving improvements in area and power efficiency across designs.
• Review verification plans and resolve RTL issues to ensure feature correctness and design integrity.
• Support SoC teams, ensuring seamless integration and high‑quality delivery of IP modules.
• Innovate and implement automated solutions to streamline coverage closure and timing convergence.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Minimum Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering, or a closely related field.
• 4-12 years of experience with a Bachelor's degree or 3-10 years of experience with a Master's degree.
• Strong expertise in RTL development using System Verilog.
• Proficiency in low‑power design techniques, including UPF, clock gating, and multiple clock domain design.
• Hands‑on experience with front‑end design tools such as Spyglass, VC Lint, CDC, and synthesis tools.
• Solid understanding of state machine design, simulation, and debugging using tools like VCS and Verdi.
• Scripting proficiency in Perl, Python, or TCL for design automation and workflow optimization.

Preferred Qualifications

• Familiarity with DFI, DDR, or LPDDR protocols and DDR PHY/Memory Controller designs.
• Basic understanding of analog design to facilitate optimal integration of analog and digital components.
• Pre‑silicon and post‑silicon validation experience is an advantage.
• Knowledge of area and power optimization techniques for IP designs.
• Strong problem‑solving skills with the ability to make critical technical decisions in complex situations.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.