Signal & Power Integrity Engineer

Intel Corporation; Bengaluru; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

Intel Corporation in Bengaluru seeks an Experienced Signal Integrity Engineer to design and optimize high-speed interconnects across boards and packages. You will apply 3D EM simulations, validate SI assumptions, and collaborate with IP teams to tighten margins and ensure product reliability.

Key focus areas include designing test structures, developing electrical specifications, and guiding platform integration while addressing attenuation, crosstalk, jitter, and power noise to meet landing

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of experience with a Bachelor's degree, 6+ years with a Master's degree, or 4 years with a PhD.
• Proficiency in signal integrity analysis, including simulations and validation techniques.
• Hands-on experience with 3D EM solvers and 3D modeling tools.
• Strong understanding of PCB and package design principles.
• Expertise in electrical validation and debug practices.
• Technical proficiency in noise glitch and signal/power integrity analysis.

Responsibilities

• Develops signal integrity solutions for large high-speed platforms and packages.
• Performs simulations of interconnects and guides physical implementation.
• Designs and characterizes test structures to correlate simulations and measurements.
• Documents electrical specifications and guidelines for customers and platforms.

Skills

Signal integrity

3D-EM solvers

PCB design

Package design

Electrical validation

Noise analysis

Education

Bachelor's degree in Electrical Engineering

MS/PhD preferred

Tools

3D EM solvers

3D modeling tools

Job description

Job Details

Delivers signal integrity solutions for large, complex highspeed platforms, boards, and packages. Develops a viable space for all interconnects including 2D and 3D models extracts of electrical structures for the entire dietodie interconnect. Defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins. Applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges. Develops electrical specifications and new industry standard interconnect specifications to guide consortiums for nextgeneration interfaces. Documents and provides implementation guidelines to the end customers as part of the platform design guide. Collaborates with IP design teams and silicon integration teams to ensure the IP and SoC designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost.

Qualifications

Minimum Qualifications

• - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• - 8+ years of experience with a Bachelor's degree, 6+ years with a Master's degree, or 4 years with a PhD.
• - Proficiency in signal integrity analysis, including simulations and validation techniques.
• - Hands-on experience with 3D EM solvers and 3D modeling tools.
• - Strong understanding of PCB and package design principles.
• - Expertise in electrical validation and debug practices.
• - Technical proficiency in noise glitch and signal/power integrity analysis.

Preferred Qualifications

• - Advanced knowledge of systems engineering fundamentals related to signal delivery design and evaluation.
• - Familiarity with DDR and SERDES interfaces, such as LPDDR5x/6, GDDR6/7, PCIe Gen5/6/7, PAM-4 SerDes, UCIe, UAL, I3C, SVID, etc.
• - Experience developing electrical interface specifications and collaborating with industry consortiums.
• - Ability to demonstrate strong problem-solving skills and strategic thinking in design optimization.
• - Proven ability to work collaboratively across multidisciplinary teams.

We are looking for passionate individuals eager to make an impact and drive innovation.

Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations:

• * Job posting details (such as work model, location or time type) are subject to change.
• * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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