Synthesis- Lead /Staff Engineer

Qualcomm; Chennai District; On-site; INR 1,500,000 - 2,700,000; Full time

Job summary

Qualcomm India Private Limited is seeking an engineer to lead synthesis and low power implementation bring up for power complex SoCs in Chennai. You will work on power-aware techniques, balance trade-offs, and collaborate with DFT and PD teams to resolve timing and low-power issues.

The role requires 7+ years of hardware engineering experience or equivalent, with strong scripting skills in TCL, Python or Perl, and experience with multi‑voltage designs. Perforce/ClearCase experience is a plus.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities

• Synthesize and implement power-aware designs for complex SoCs.
• Collaborate with PD and DFT teams to enable MBIST and scan insertion.
• Address pre-layout timing challenges and provide constraint feedback to design teams.
• Perform pre/post-layout netlist low power qualification for SoC and subsystems.

Skills

Synthesis

Power aware design

Timing constraints

DFT/MBIST

Scripting TCL/Python

Education

Bachelor's degree in CS/EE

Master's degree

PhD

Tools

Perforce

ClearCase

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

In this position, the engineer will be responsible for Synthesis and low power implementation bring up of power complex SoC

• Knowledgeable with physical and power aware synthesis techniques, and fluent with multi voltage designs
• Knowledgeable with balancing between power, performance, area and verification priority approaches at synthesis
• Work with design to bring out pre layout timing challenges and constraint feedback
• Proficient with pre and post layout netlist low power qualification for SoC flat and Sub system level
• Closely collaborate with DFT team for enabling latest MBIST and DFT scan insertion
• Closely work with Physical Design (PD) to bring out low power implementation issues and fixes
• Proficient in scripting languages (TCL, Perl, Python, shell)

In addition, below experience will be a value add

• Good knowledge on design data management aspects such as perforce and clearcase
• Logical equivalence check between RTL to Netlist and Netlist to Netlist
• Knowledgeable with physical and power aware implementation techniques, and fluent with multi voltage designs
• Knowledgeable with lower tech node timing derating and
• Mentoring junior engineers in different areas of timing flows and methodologies

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

7+ yrs of experience

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