Synthesis- Lead /Staff Engineer

Nutanix; Chennai District; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Qualcomm India Private Limited in Chennai is seeking an engineer for synthesis and low power implementation bring-up of a power-optimized SoC.

The role involves balancing power, performance and area, contributing to pre-layout timing, DFT/MBIST integration, and collaboration with PD and design teams; proficiency in TCL, Perl, Python, and shell is required.

Qualifications

• Bachelor's degree in CS/Electrical/Engineering and 3+ years Hardware Engineering or related work experience.
• Master's degree in CS/Electrical/Engineering and 2+ years Hardware Engineering or related work experience.
• PhD in CS/Electrical/Engineering and 1+ year Hardware Engineering or related work experience.

Responsibilities

• Synthesis and low power implementation bring up of power complex SoC.
• Balance between power, performance, area and verification priorities at synthesis.
• Work with design to address pre-layout timing challenges and constraint feedback.
• Proficient in pre/post layout netlist low power qualification for SoC and sub-systems.
• Collaborate with DFT team for MBIST and DFT scan insertion.
• Work with Physical Design to resolve low power implementation issues.
• Proficient in scripting (TCL, Perl, Python, shell).

Skills

Scripting languages

Power aware synthesis

Timing constraints

Education

Bachelor's degree in Computer Science or E/E Engineering

Master's degree in Computer Science or E/E Engineering

PhD in Computer Science or E/E Engineering

Tools

Perforce

ClearCase

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

In this position, the engineer will be responsible for Synthesis and low power implementation bring up of power complex SoC

• Knowledgeable with physical and power aware synthesis techniques, and fluent with multi voltage designs
• Knowledgeable with balancing between power, performance, area and verification priority approaches at synthesis
• Work with design to bring out pre layout timing challenges and constraint feedback
• Proficient with pre and post layout netlist low power qualification for SoC flat and Sub system level
• Closely collaborate with DFT team for enabling latest MBIST and DFT scan insertion
• Closely work with Physical Design (PD) to bring out low power implementation issues and fixes
• Proficient in scripting languages (TCL, Perl, Python, shell)

Additional Experience (value add)

• Good knowledge on design data management aspects such as perforce and clearcase
• Logical equivalence check between RTL to Netlist and Netlist to Netlist
• Knowledgeable with physical and power aware implementation techniques, and fluent with multi voltage designs
• Knowledgeable with lower tech node timing derating and
• Mentoring junior engineers in different areas of timing flows and methodologies

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

7+ yrs of experience

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