High Performance DSP core Implementation(Synthesis) Senior Lead Engineer

Qualcomm; Dadri; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Qualcomm India Private Limited is seeking an experienced ASIC Engineer to define, model, design, verify, and document IP and block/SoC development for high-performance, low-power products.

You will collaborate with cross-functional teams to determine the product execution path, focusing on synthesis, timing closure, and low-power techniques using UPF, with scripting in Python/Tcl.

Qualifications

• Bachelor's degree in science/engineering with 3+ years ASIC experience.
• Master's degree with 2+ years ASIC experience.
• PhD with 1+ year ASIC experience.
• 5–8 years hands-on experience in Synthesis and LEC.

Responsibilities

• Strong understanding of Physical Synthesis and methodologies.
• Write timing constraints for synthesis, STA, and timing closure.
• Timing closure for multi-clock domain designs.
• Familiar with MCMM synthesis and optimization.
• Low-power design implementation using UPF.
• Scripting in Perl/Python, TCL.
• Collaborate with design/DFT/PD teams for netlist delivery.
• Handle ECOs and formal verification with high-quality matrices.

Skills

Python/Tcl

Synthesis Tools

LEC/LP Signoff

Verilog/VHDL Synthesis

Software Dev Practices

Motivation/Commitment

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Fusion Compiler

Genus

UPF

MCMM synthesis

Job description

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Experience:

5 to 8 years of hands on experience in Synthesis and LEC

Job Role

• Should have strong understanding and in depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
• Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
• Experience in all aspects of timing closure for multi-clock domain designs.
• Should be familiar with MCMM synthesis and optimization.
• Should have good understanding of low-power design implementation using UPF.
• Experience with scripting language such as Perl/ Python, TCL.
• Experience with different power optimization flows or technique such as clock gating.
• Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
• Should be able to handle ECOs and formal verification and maintain high quality matrix

Skill Set

• Proficiency in Python/Tcl
• Familiar with Synthesis tools (Fusion Compiler/Genus)
• Fair knowledge in LEC, LP signoff tools
• Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
• Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus
• Should be sincere, dedicated and willing to take up new challenges

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