Synthesis- Lead /Staff Engineer Chennai, Tamil Nādu, India Hardware Engineering Posted 18 hours ago

Qualcomm; Chennai District; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Qualcomm India Private Limited is seeking an experienced hardware engineer to lead synthesis and low power bring-up for power-sensitive SoCs. You will balance power, performance and area, address pre-layout timing, and qualify netlists for low power at multiple levels.

Collaboration with DFT and Physical Design teams is essential, and scripting in TCL/Perl/Python will be used daily. The role requires strong technical leadership, 7+ years of hardware experience, and a degree in engineering or

Qualifications

• Bachelor's degree or higher in CS/EE/Engineering or related field with 3+ years hardware engineering experience.
• Master's degree with 2+ years hardware engineering experience.
• PhD with 1+ year hardware experience.

Responsibilities

• Synthesis and low power implementation bring up of power complex SoC.
• Balance between power, performance, and area with verification priorities.
• Work with design to address pre-layout timing challenges.
• Proactively qualify pre/post layout netlists for low power at IP/SoC levels.
• Collaborate with DFT team for MBIST/DFT insertion.
• Coordinate with Physical Design to resolve low power implementation issues.
• Proficient in TCL, Perl, Python, and shell scripting.

Skills

Synthesis

Low power design

Power aware

Multi voltage designs

Timing constraints

Pre/post layout timing

Netlist low power qualification

DFT & MBIST

Physical Design collaboration

Scripting (TCL)

Scripting (Python)

Scripting (Perl)

Scripting (Shell)

Education

Bachelor's degree in CS/EE/Engineering

Master's degree in CS/EE/Engineering

PhD in CS/EE/Engineering

Tools

Perforce

ClearCase

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

In this position, the engineer will be responsible for Synthesis and low power implementation bring up of power complex SoC

• Knowledgeable with physical and power aware synthesis techniques, and fluent with multi voltage designs
• Knowledgeable with balancing between power, performance, area and verification priority approaches at synthesis
• Work with design to bring out pre layout timing challenges and constraint feedback
• Proficient with pre and post layout netlist low power qualification for SoC flat and Sub system level
• Closely collaborate with DFT team for enabling latest MBIST and DFT scan insertion
• Closely work with Physical Design (PD) to bring out low power implementation issues and fixes
• Proficient in scripting languages (TCL, Perl, Python, shell)

In addition, below experience will be a value add

• Good knowledge on design data management aspects such as perforce and clearcase
• Logical equivalence check between RTL to Netlist and Netlist to Netlist
• Knowledgeable with physical and power aware implementation techniques, and fluent with multi voltage designs
• Knowledgeable with lower tech node timing derating and
• Mentoring junior engineers in different areas of timing flows and methodologies

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

7+ yrs of experience

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