Synthesis & Front-End Implementation Engineer

NXP Semiconductors NV; Pune District; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

NXP Semiconductors NV in Pune is seeking a highly motivated Synthesis & Front-End Implementation Engineer. You will translate RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

Responsibilities include RTL synthesis, timing constraint development, STA and timing closure, formal verification, power/area optimization, and close collaboration with RTL, DFT, and physical-design teams.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or a related field.
• 5+ years in digital ASIC/SoC design with focus on synthesis and front-end implementation.
• Experience with industry-standard synthesis and verification tools is required.
• Strong knowledge of Verilog/SystemVerilog and STA concepts.

Responsibilities

• Perform RTL synthesis for digital blocks and sub-systems including hierarchical synthesis.
• Develop and implement timing constraints (SDC) to meet target frequencies.
• Conduct STA, identify critical paths, and assist with timing closure.
• Execute formal verification to ensure equivalence between RTL and netlists.
• Analyze power at front-end and optimize using power analysis tools.
• Estimate and optimize area to meet chip size targets.
• Collaborate with RTL designers, DFT, and physical design teams for hand-off.
• Develop automation scripts (Tcl, Python, Perl) for flows and analysis.
• Evaluate new CAD tools and methodologies to improve efficiency.
• Document design constraints, methodologies, and results thoroughly.

Skills

Verilog / SystemVerilog

Scripting (Tcl, Python, Perl)

Problem solving

Communication skills

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Synopsys Fusion Compiler

Synopsys PrimeTime

Cadence Conformal (LEC)

Job description

We are seeking a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.

Job Responsibilities

• Performing synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.
• Developing and implementing robust timing constraints (SDC) to achieve target frequencies and optimize design performance.
• Conducting STA, identifying critical paths, and collaborating with design teams for timing closure.
• Executing formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists.
• Analyzing and optimizing power consumption at the front-end stage, utilizing power analysis tools and techniques.
• Performing area estimation and optimization to meet aggressive chip size requirements.
• Collaborating closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.
• Developing and maintaining automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.
• Evaluating and integrating new CAD tools and methodologies to improve efficiency and design quality.
• Documenting design constraints, methodologies, and analysis results thoroughly.

Job Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of relevant experience in digital ASIC/SoC design, with a focus on synthesis and front-end implementation.
• Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler, Synopsys Fusion Compiler or similar).
• Strong understanding of static timing analysis (STA) concepts and tool (e.g., Synopsys PrimeTime).
• Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)).
• Understanding of upf, low-power design techniques and power analysis concepts.
• Solid knowledge of Verilog/System verilog for digital design.
• Familiarity with scripting languages (Tcl, Python, Perl) for automation.
• Knowledge of DFT (Design for Testability) principles is a plus.
• Excellent problem-solving skills and attention to detail.
• Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment across multiple time zones.