Physical Design- Sr Staff Engineer

Qualcomm; Chennai District; On-site; INR 3,500,000 - 7,500,000; Full time

Job summary

Qualcomm India Private Limited in Chennai seeks a Synthesis (Design Implementation) Engineer to drive synthesis and low‑power implementation for complex SoC designs. You will work with Design, Physical Design, DFT and Timing teams to achieve PPA targets on advanced nodes.

Lead synthesis deliverables, mentor team on timing closure and UPF methods, and push flow improvements and automation to accelerate tape‑out while maintaining quality and schedule.

Qualifications

• Bachelor's degree or higher in a relevant engineering field.
• 6+ years of Hardware Engineering or related work experience for Bachelor's.
• Experience with synthesis for complex SoCs and advanced nodes.

Responsibilities

• Lead and manage synthesis deliverables across blocks/subsystems with schedule and tape-out commitments.
• Mentor team on timing closure, UPF methodologies, and low-power implementation challenges.
• Drive execution reviews, risk assessment, and closure plans for project milestones.
• Coordinate RTL, DFT, Physical Design, STA, and Verification to resolve cross-functional issues.
• Define synthesis methodologies and flow improvements; drive automation and tooling.
• Contribute to resource planning and prioritization of team deliverables.

Skills

Synthesis

UPF

Low power

Timing closure

Python scripting

Shell scripting

Mentoring

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering

PhD in Computer Science, Electrical/Electronics Engineering, Engineering

Tools

Fusion Compiler

Cadence Genus

Design Compiler

PrimeTime/Tempus

UPF/Conformal tools

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Qualcomm Chennai is seeking a highly motivated Synthesis (Design Implementation) Engineer to drive synthesis and low‑power implementation for complex SoC and subsystem designs. The candidate will work closely with Design, Physical Design, DFT, and Timing teams to achieve competitive Power, Performance, and Area (PPA) targets on advanced technology nodes.

Key Responsibilities

• Lead and manage synthesis deliverables across multiple blocks/subsystems, ensuring schedule, quality, and tape‑out commitments are met.
• Mentor and technically guide team members on timing closure, UPF methodologies, advanced‑node implementation challenges, and debug strategies.
• Drive execution reviews, risk assessment, and closure plans for project milestones.
• Coordinate across RTL, DFT, Physical Design, STA, and Verification teams to resolve cross‑functional issues and improve design convergence.
• Define and drive synthesis methodologies, best practices, and flow improvements across the team.
• Contribute to resource planning, execution tracking, and prioritization of team deliverables.
• Run quality checks including check_design, check_timing, Lint, CDC, ERC, and support MTBF‑related fixes.

Required Skills

• Strong experience with Physical and low power aware synthesis using Synopsys Fusion Compiler/Design Compiler or Cadence Genus.
• Implement and validate UPF‑based low‑power architectures, including isolation cells, level shifters, retention cells, and power switches.
• Develop and maintain SDC constraints, perform Pre‑STA analysis, and drive pre‑layout timing convergence.
• Expertise in PrimeTime/Tempus, UPF, CLP, and Formality/Conformal/Conformal ECO.
• Good understanding of multi‑voltage designs, low‑power methodologies, and timing closure.
• Develop automation and flow improvements using AI agents, TCL, Perl, Python, and Shell scripting.

Preferred Qualifications

• Experience on advanced nodes (6nm/5nm/4nm/3nm or equivalent).
• Ownership of synthesis for blocks/subsystems with 2M+ cells.
• Expertise in UPF, Multi voltage Designs, POCV/AOCV and variation‑aware high speed timing analysis.
• Experience with flat‑level signoff flows, LEC, CLP and physical synthesis methodologies.
• Ability to independently drive synthesis and low‑power closure through tape‑out.
• IO timing closure.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Equal Opportunity and Accessibility

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] for reasonable accommodations.