Synthesis Engineer, Principal

Qualcomm; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks an experienced hardware engineer with deep expertise in synthesis and timing closure. You will drive physical synthesis, write timing constraints, and collaborate with DFT and PD teams to ensure robust netlist delivery for multi-clock designs.

The role demands 15+ years of hardware experience and advanced degrees; you will work across hardware groups to optimize power with UPF and implement ECOs, aiming for high-quality timing closure and

Qualifications

• Strong understanding of physical synthesis and timing closure.
• Experience writing timing constraints for synthesis, STA, and pipelining.
• Expertise in multi-clock domain timing closure.
• Familiar with UPF-based low-power design.
• Proficient in scripting languages (Perl, Python, TCL).
• Ability to work with design, DFT and PD teams.
• Experience handling ECOs and formal verification.

Skills

Physical Synthesis

Timing constraints

Timing closure

MCMM synthesis

Low-power design UPF

Scripting (Perl/Python/TCL)

Power optimization / clock gating

Netlist delivery coordination

ECOs & formal verification

15+ years experience

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Description

Job Description:

• Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
• Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
• Experience in all aspects of timing closure for multi-clock domain designs.
• Should be familiar with MCMM synthesis and optimization.
• Should have good understanding of low-power design implementation using UPF.
• Experience with scripting language such as Perl/ Python, TCL.
• Experience with different power optimization flows or technique such as clock gating.
• Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
• Should be able to handle ECOs and formal verification and maintain high quality matrix
• 15+ yrs experience

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

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