Subsystem & Protocol DV Lead

Anthriq; Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Anthriq is seeking an experienced memory-subsystem verification engineer in Bengaluru to advance our signal-processing infrastructure stack. You will design UVM-based testbenches, implement protocol checkers and error-injection benches for die-to-die links, and ensure full coverage of complex memory controllers.

The role requires deep expertise in LPDDR4/5 interconnects, CDC verification, and a track record of mentoring junior engineers while delivering deterministic validation results on time.

Qualifications

• 8+ years verifying memory controllers (LPDDR4/5/5X) or high-speed interconnect protocols and DMA engines.
• Credit-based flow control, arbitration, memory-map region protection.
• UVM architecture, constrained-random stimulus, functional-coverage modeling.
• Link-layer packetization, retry, framing FSM verification.
• Clock-Domain-Crossing (CDC) verification.

Responsibilities

• Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA.
• Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link layer, incl. cross-die fail-stop.
• Verify hardware synchronization barriers and multi-client arbitration scoreboards.
• Own test-plan execution, mentor junior engineers, drive block coverage to 100%.

Skills

UVM

Memory controller verification

LPDDR4/5/5X

CDC verification

HDL/SystemVerilog

Tools

Cadence Xcelium

vManager

Indago

Job description

About The Company

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.

Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.

Anthriq Silicon is our ground-up effort to build a new compute category.

Key Responsibilities

• Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA.
• Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link layer, incl. cross-die fail-stop.
• Verify hardware synchronization barriers and multi-client arbitration scoreboards.
• Own test-plan execution, mentor junior engineers, drive block coverage to 100%.

Must-have Skills

• 8+ years verifying memory controllers (LPDDR4/5/5X) or high-speed interconnect protocols and DMA engines.
• Credit-based flow control, arbitration, memory-map region protection.
• UVM architecture, constrained-random stimulus, functional-coverage modeling.
• Link-layer packetization, retry, framing FSM verification.
• Clock-Domain-Crossing (CDC) verification.

Nice-to-have

• Multi-die / die-to-die (UCIe-class or proprietary) link experience.
• PHY-to-MAC protocol simulation.

Target EDA tools:

Cadence Xcelium, vManager, Indago

Skills: arbitration,infrastructure,high-speed interconnect,flow control,credit,signal,barriers,clock-domain-crossing,flow,vmanager,indago,architecture,cdc,protocol,memory-subsystem