RTL Design Engineer — Silicon Team

Anthriq; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Anthriq in Bengaluru is seeking RTL engineers to work on a compute-heavy multi-core vector processor. You will implement critical paths, build switch fabrics, and integrate DDR controllers.

The ideal candidate should have over 5 years of RTL design experience in SystemVerilog and strong digital design fundamentals. This role offers a chance to own your work from spec to synthesis to verification in a small team setting.

Qualifications

• 5+ years RTL design in SystemVerilog.
• Strong digital design fundamentals, able to design from spec.
• Comfortable in a small team environment with ownership.

Responsibilities

• Implement execution units and critical arithmetic paths.
• Build multi-stage switch fabric and high-speed serial interfaces.
• Integrate DDR controller and build JTAG debug controller.

Skills

RTL design in SystemVerilog

Digital design fundamentals

Pipeline control

SoC integration

Synthesis

Timing closure

Job description

About Anthriq

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human‑aware technology from custom analog front‑end IP that captures biosignals at the source, to signal‑first compute systems built for time‑critical workloads.

Anthriq Silicon is our ground‑up effort to build a new compute category—a custom ISA, a frontier signal‑processing chip, and a full toolchain designed alongside the silicon. Every layer is being built, not assembled. anthriq.com/silicon

About The Role

We're building a compute‑heavy multi‑core vector processor with a custom ISA, and we're hiring RTL engineers across multiple domains. You don't need to cover everything — we want engineers who go deep in at least one area and can grow into adjacent ones.

When You Apply, Tell Us Your Primary Strength

• Datapath — execution units, register files, floating‑point arithmetic
• Fabric & Interconnect — on‑chip networks, PCIe, high‑speed serial, CDC
• Pipeline Control — scoreboards, dispatch logic, DMA, CSR
• Orchestration & Integration — SoC top‑level, AXI bus fabric, system controller
• Peripherals & Security — DDR controller, secure boot, JTAG, trace
• Performance & PPA — synthesis, timing closure, power analysis

What You'll Work On

Datapath

Implement execution units (integer, FP, fixed‑point, complex), multi‑port register files, bypass/forwarding networks, IEEE 754‑compliant FP datapaths, and critical arithmetic paths (carry‑save adders, Wallace trees, Booth multipliers).

Fabric & Interconnect

Build a multi‑stage switch fabric with credit‑based flow control, high‑speed serial interfaces (8b/10b, CRC, ARQ), PCIe Gen3 x16 endpoint, and all clock domain crossing logic.

Pipeline Control

Implement the instruction scoreboard, dispatch logic, pipeline drain/flush FSMs, multi‑channel DMA controller, AXI‑Stream IO FIFOs, and CSR register file.

Orchestration & Integration

Build the RISC‑V‑based system management controller, AXI4‑Lite multi‑master bus infrastructure, and own top‑level chip integration across all blocks, clocks, and resets.

Peripherals & Security

Integrate DDR4 memory controller, implement silicon root‑of‑trust/secure boot/key management, build JTAG debug controller (IEEE 1149.1), and trace aggregation unit.

Performance & PPA

Run synthesis continuously from early RTL, identify and resolve critical timing paths, run power estimation from switching activity, and maintain weekly PPA dashboards with Tcl/Python scripts.

Requirements

• 5+ years RTL design in SystemVerilog
• Strong digital design fundamentals, you design from spec, not from templates
• Comfortable in a small team where ownership is real and total

Why This Role

This is not an integration job. You write RTL that ships in silicon. You own your block end‑to‑end from spec to synthesis to verification sign‑off. The team is small, the problem is genuinely hard, and the work is built to last.

Skills: signal, dsp, soc, pipeline, datapath, arithmetic, integration, ppa, design, axi, synthesis, boot, timing closure, silicon