Staff Engineer, Design Verification Engineering

Analog Devices; Kolkata District; On-site; INR 2,400,000 - 4,000,000; Full time

Job summary

Analog Devices is seeking a senior design verification engineer with 6–10 years of experience to architect and implement robust DV environments. You will work on complex IPs and processor subsystems, using UVM and Formal verification to drive coverage and validation across multiple teams in India.

This role emphasizes collaboration, debugging and scalable DV design. The ideal candidate translates DV requirements into comprehensive test plans and integrates block level tests into system

Qualifications

• B.E./B.Tech in Electrical/Electronics/CS is required.
• 6–10 years of design verification experience with UVM and constrained random approaches.
• Strong understanding of DV concepts and scalable DV environment architectures.
• Experience translating DV requirements into robust DV environments and coverage metrics.
• Experience with AI tools in DV and ability to map end applications to test plans.

Responsibilities

• Verify complex designs such as accelerators, data path IPs, and processor cores using UVM and Formal DV.
• Architect the testbench and verification environment in UVM and Formal approaches.
• Define test plans, tests and verification methodology for block/sub-system level verification; integrate block testbenches at subsystem level UVM.
• Package verification environment for Digital IP for integration across execution stages.
• Evaluate 3rd party IPs and establish benchmarking flows for DV evaluation.
• Build expertise on interfaces/protocols like DDR, Ethernet, PCIe, HDMI, MIPI, etc.
• Support post-silicon verification with design, product evaluation and applications teams.

Skills

UVM

Constrained random

Coverage-based DV

Formal verification

DV environment architecture

Debugging

Teamwork

Communication

APB/AHB/AXI knowledge

SoC/ASIC DV

Education

B.E./B.Tech in Electrical/Electronics/CS

Tools

SystemVerilog

UVM

Formal verification tools

Job description

Job Responsibilities

• Verification of complex designs such as accelerators/data path IP, processor core subsystems, complex interfaces/protocols such as DDR/Ethernet/USB etc using leading edge methodologies like UVM & Formal DV
• Architect the testbench and develop the verification environment in UVM and Formal based verification approaches
• Define test plan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects
• Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution
• Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home‑grown & 3rd party IPs for consistent benchmarking of DV evaluation
• Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
• Support post‑silicon verification activities of the products working with design, product evaluation and applications engineering team

Position Requirements

• Minimum B.E./ B.Tech degree in Electrical/Electronics/Computer science
• 6 - 10 years experience in design verification with UVM and constrained random, coverage‑based verification approaches
• Strong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success
• Experience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergence
• Experience with AI tools in DV
• Adaptability to learn end application/systems and map into smart verification test plans
• Excellent debugging and analytical skills
• Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically
• Knowledge of Assertion based formal verification
• Understanding of standard on‑chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus
• Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus
• Experience with ASIC/ SoC product DV & productization is very desirable

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.