RTL Engineer Peripherals & Security

Anthriq; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Anthriq in Bengaluru is seeking an experienced engineer to build a compute-heavy multi-core vector processor. You will be responsible for implementing the memory controller, security subsystem, and debug infrastructure.

Ideal candidates have 5+ years of RTL design experience in SystemVerilog and must have a strong background in memory controller integration and security hardware. This role offers exciting challenges in a cutting-edge technology environment.

Qualifications

• 5+ years RTL design in SystemVerilog.
• Experience with DDR memory controller integration.
• Knowledge in security hardware: secure boot and lifecycle management.
• Familiarity with JTAG / IEEE 1149.1 implementation.

Responsibilities

• Integrate the DDR4 memory controller.
• Implement the security subsystem.
• Build the trace aggregation unit.
• Implement the JTAG debug controller.
• Build the clock/reset unit.
• Integrate vendor IP with custom wrapper modules.

Skills

RTL design in SystemVerilog

DDR memory controller integration

Security hardware experience

JTAG / IEEE 1149.1 implementation

Mixed vendor-IP + custom-logic integration

PLL configuration

Clock distribution

Job description

About The Company

Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.

Read More About Anthriq Silicon Program here: anthriq.com/silicon

About The Role

We are building a compute-heavy multi-core vector processor with a custom ISA. You will implement the memory controller, security subsystem, debug infrastructure, trace unit, and clock/reset unit.

Responsibilities

• Integrate the DDR4 memory controller: deterministic DDR memory controller integration, vendor PHY IP, flash boot engine
• Implement the security subsystem: silicon root-of-trust IP integration, secure boot, key management, lifecycle state management, scan chain gating
• Build the trace aggregation unit: multi-source event collection, ring buffer, filtering, host readout interface
• Implement the JTAG debug controller: IEEE 1149.1 TAP state machine, debug module interface, system-wide halt
• Build the clock/reset unit: PLL configuration, phased reset sequencer, per-core clock gating cells
• Integrate vendor IP (DDR PHY, SerDes PHY, PLL) with custom wrapper modules

Requirements

• 5+ years RTL design in SystemVerilog
• DDR memory controller integration (DDR3 or DDR4, vendor PHY IP)
• Security hardware experience: secure boot, OTP, key storage, lifecycle management
• JTAG / IEEE 1149.1 implementation
• Mixed vendor-IP + custom-logic integration
• PLL configuration and clock distribution

Nice to Have

• HMAC-SHA256 or other hash engine implementation
• Trace/debug infrastructure design (ARM CoreSight-like)
• Anti-tamper or anti-rollback mechanisms
• Production test interface experience (BIST, scan)

Skills: phy,ddr,rtl design,infrastructure,isa,asic,ip,trace,boot,integration,design,security