RTL Engineer Pipeline Control

Anthriq; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A tech infrastructure company in Bengaluru seeks an experienced engineer for high-performance signal processing ASIC development. The role involves implementing key pipeline control logic components and requires at least 3 years of RTL design experience in SystemVerilog, along with strong knowledge in DMA controller and AXI protocols. Ideal candidates will be skilled in hazard detection and state machine designs, contributing to innovative technology that responds to human intent.

Qualifications

• 3+ years of RTL design experience in SystemVerilog.
• Experience with pipeline control logic (hazard detection, bypassing).
• Experience with FSM-heavy designs (complex state machines).
• Experience with DMA or memory controller design.
• Familiarity with AXI protocol (AXI4-Lite, AXI4-Stream).

Responsibilities

• Implement the instruction scoreboard for hazard detection and tracking.
• Build the dispatch logic for partial issue and dependency resolution.
• Implement DMA controller for multi-channel transfers.
• Develop IO port FIFOs with AXI-Stream interfaces.
• Work with the verification team on pipeline corner cases.

Skills

RTL design in SystemVerilog

Pipeline control logic

FSM design experience

DMA controller design

AXI protocol experience

Job description

About The Company

Anthriq builds foundational infrastructure for human‑aware technology. Our Human Body API captures, decodes, and translates biosignals, brain, muscle, and physiological data into real‑time, programmable applications. With a modular, end‑to‑end platform, we enable teams to move from signal capture to deployment without reinventing the stack powering a future where technology responds to human intent, not interfaces.

About The Role

We are building a high‑performance signal processing ASIC—a multi‑core vector processor with a custom ISA. You will implement the pipeline control logic: the scoreboard, dispatch, hazard detection, DMA controller, and IO subsystem that orchestrate instruction flow through the processor core.

Responsibilities

• Implement the instruction scoreboard (hazard detection, credit tracking, stall generation)
• Build the dispatch logic (partial issue, slot ordering, multi‑slot dependency resolution)
• Implement pipeline drain and flush FSMs (clean shutdown, exception handling, restart)
• Build the DMA controller (multi‑channel, multi‑dimensional transfers, scatter‑gather)
• Implement IO port FIFOs with AXI‑Stream interfaces and credit‑based backpressure
• Implement the program counter unit (hardware loops, segment management, prefetch control)
• Build the CSR register file (read/write/set/clear access policies, performance counters)
• Work with the verification team on pipeline corner cases

Requirements

• 3+ years RTL design in SystemVerilog
• Pipeline control logic experience (scoreboard, hazard detection, bypassing)
• FSM‑heavy design experience (complex state machines with multiple interacting FSMs)
• DMA controller or memory controller design
• AXI protocol experience (AXI4‑Lite, AXI4‑Stream)
• Comfortable with credit‑based flow control and backpressure mechanisms

Nice to Have

• Processor pipeline design (in‑order or out‑of‑order)
• VLIW dispatch logic (multi‑slot issue, partial issue)
• Hardware loop implementation experience
• Real‑time/deterministic design constraints

Skills: fsms, credit, flow, axi, control logic, interfaces, pipeline, io, instruction, design