Principal Engineer – Static Timing Analysis (STA)

TylSemi, Inc.; Karnataka; Hybrid; INR 4,500,000 - 7,000,000; Full time

Job summary

TYLsemi, Inc. is seeking a highly experienced Principal Engineer – STA to lead timing analysis for advanced ASIC/SOC designs.

You will drive end-to-end STA, timing signoff, and convergence across multi-clock and multi-voltage designs, partnering with RTL, PD, DFT, CTS, and CAD teams. The role demands deep expertise in setup/hold, CTS interaction, and advanced node effects, with strong leadership and mentoring capabilities.

Qualifications

• Lead end-to-end STA and timing signoff for full-chip and subsystem designs.
• Define timing constraints and validate SDCs for robust timing closure.
• Collaborate with RTL, Physical Design, DFT, CTS, and CAD teams.
• Mentor engineers and lead technical reviews for signoff readiness.
• Experience with 7nm/5nm or below technology nodes is a plus.

Responsibilities

• Lead end-to-end STA and timing signoff activities for full-chip and subsystem designs.
• Drive timing closure across setup, hold, SI, noise, crosstalk, and MMMC scenarios.
• Define timing constraints, validate SDCs, and ensure robust methodology execution.
• Collaborate with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence.
• Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

Skills

STA expertise

Timing signoff

Leadership

Scripting (Tcl, Python)

Education

Bachelor's/Master's in Electronics or EEE/VLSI

Tools

Synopsys PrimeTime

Tempus

StarRC

Job description

Principal Engineer – Static Timing Analysis (STA)

About this position

About TYLsemi, Inc.

The Opportunity

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead.2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.Translation:We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.No endless meetings, no PowerPoint presentations to convince middle management.Remote-Friendly, Global TeamUS team:Bay Area preferred, but we hire the best people regardless of locationIndia team:Building a world-class design center in BangaloreMove Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We ValueOwnership mindset.You're not here to execute someone else's roadmap. You're here to define it.Bias for action.We move fast. Analysis paralysis doesn't fly here.Deep technical expertise.This is hard engineering. We need people who've shipped real silicon and debugged real hardware.Low ego, high standards.We don't care about titles or politics. We care about results.The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.The team has done this before.We've built and exited semiconductor companies at scale. This isn't our first rodeo.The traction is de-risked.We have LOIs, strategic investors, and a clear path to revenue.The work is consequential.You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet.Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We areseekinga highly experienced Principal Engineer – STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deepexpertisein static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology nodes.1

WhatYou’llDo

Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs.Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios.Define timing constraints, validate SDCs, and ensure robust timingmethodologyexecution.Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence.Analyze and resolve complex timing violations and critical path bottlenecks.Support ECO implementation and signoff verification for advanced node tape-outs.Develop and improve automation flows, scripts, timing dashboards, andmethodologyenhancements.Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

WhatWe’reLooking For

15+ years of experience in STA and timing signoff for ASIC/SOC programs.Bachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field.Strongexpertisein setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques.Hands-on experience with SynopsysPrimeTime, Tempus,StarRC, and related signoff tools.Strong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects.Experience with advanced technology nodes such as 7nm, 5nm, or below.Strong scripting skills inTcl, Python, Perl, or Shell scripting.Excellent technical leadership, debugging, communication, and stakeholder management skills.

Good to Have

Experience with package-aware timing analysis and chiplet architectures.Exposure toAI/ML-driven timing optimization methodologies.Familiarity with automotive or high-reliability SOC design standards.

Success in This Role Looks Like

Successful timing closure and signoff delivery for complex SOC tape-outs.Efficient management of timing convergence with minimal ECO impact.Improved STAmethodologyscalability, automation, and execution efficiency.Strong technical influence, mentoring contribution, and cross-functional leadership.