Staff Engineer – Static Timing Analysis (STA)

TYLsemi; India; Hybrid; INR 3,500,000 - 5,000,000; Full time

Job summary

TYLsemi is seeking an experienced Staff Engineer – Static Timing Analysis (STA) to lead timing analysis and signoff for complex SoCs and advanced-node designs in Bengaluru. You will drive timing closure across blocks and full chips, collaborating with cross-functional implementation teams and contributing to STA methodology improvements.

The ideal candidate has 7+ years in STA or signoff, hands-on experience with Synopsys PrimeTime, and strong scripting skills.

Qualifications

• 7+ years in STA, timing closure, or Physical Design signoff roles
• Strong understanding of OCV/AOCV/POCV, SI/noise analysis, clocking methodologies
• Hands-on experience with PrimeTime and advanced timing signoff flows
• Good understanding of synthesis, CTS, P&R, extraction, and ECO implementation flows
• Strong scripting skills in Tcl, Perl, Python, or Shell for automation

Responsibilities

• Lead block-level and full-chip STA activities including setup, hold, recovery, removal, and noise analysis
• Drive timing closure across multiple modes and corners using MMMC methodologies
• Analyze and debug complex timing violations with synthesis, CTS, P&R, and ECO teams
• Define and validate timing constraints including SDC generation, timing exceptions, and clock definitions
• Perform timing signoff using industry-standard STA tools and methodologies
• Drive ECO implementation and timing optimization focusing on performance, power, and area trade-offs
• Contribute to automation, methodology enhancement, and flow optimization initiatives

Skills

STA expertise

Timing closure

Scripting (Tcl, Python, Perl)

Synopsys PrimeTime

Synthesis/PSC flows

Education

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline

Tools

Synopsys PrimeTime

Place‑and‑Route tools

Job description

We are seeking an experienced Staff Engineer – Static Timing Analysis (STA) to lead timing analysis and signoff activities for complex SoC and advanced-node designs. In this role, you will drive timing closure across multiple blocks and full-chip designs, collaborate with cross-functional implementation teams, and contribute to STA methodology improvements. The ideal candidate should possess strong expertise in timing signoff, MMMC analysis, and advanced timing optimization techniques.

What You’ll Do

• Lead block-level and full-chip STA activities including setup, hold, recovery, removal, and noise analysis
• Drive timing closure across multiple modes and corners using MMMC methodologies
• Analyze and debug complex timing violations in collaboration with synthesis, CTS, P&R, and ECO teams
• Define and validate timing constraints including SDC generation, timing exceptions, and clock definitions
• Perform timing signoff using industry-standard STA tools and methodologies
• Drive ECO implementation and timing optimization with focus on performance, power, and area trade-offs
• Contribute to automation, methodology enhancement, and flow optimization initiatives

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline
• 7+ years of experience in STA, timing closure, or Physical Design signoff roles
• Strong understanding of STA concepts including OCV/AOCV/POCV, SI/noise analysis, clocking methodologies, and timing exceptions
• Hands‑on experience with Synopsys PrimeTime and advanced timing signoff flows
• Good understanding of synthesis, CTS, place-and-route, extraction, and ECO implementation flows
• Strong scripting skills in Tcl, Perl, Python, or Shell for automation and productivity improvement

Good to Have

• Experience with advanced-node technologies such as 7nm, 5nm, or below
• Exposure to low-power design methodologies including UPF/CPF and power‑aware STA
• Experience in full-chip timing convergence and successful tapeout execution for large SoC designs

Success in This Role Looks Like

• Achieving timing closure with robust signoff quality across all operating modes and corners
• Efficient resolution of complex timing issues with optimized performance, power, and area impact
• Improved STA productivity through automation and methodology enhancements
• Successful collaboration across implementation and signoff teams leading to timely tapeout execution

Location

Hybrid / On-site – Bengaluru / Remote - India

About TylSemi, Inc. The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

Why Now

The Market Window

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation

We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world‑class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

But if you're the kind of person who wants to take the shot, we'd love to talk.