Senior Staff Engineer Digital Design

Infineon Technologies AG; Bengaluru; On-site; INR 300,000 - 550,000; Full time

Benefits offered by this job

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Job summary

Infineon Technologies AG in India is seeking a Senior Physical Design and Timing Closure engineer to drive die area, performance and power goals for IoT and MCU oriented SoCs.

You will lead floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, IR drop checks and physical verification, with emphasis on multi-Voltage island techniques.

Qualifications

• Bachelor's or Master's degree with specialization in VLSI design.
• 8+ years hands-on experience in physical design and timing closure of SoCs.
• Experience with industry standard tools for physical design and signoff.
• Experience in scripting languages (shell, perl, tcl) and Make flow.
• Understanding of 40nm/28nm/22nm technologies and associated PD challenges.
• Good team player with a desire to learn and explore.
• Strong commitment and determination in the area of expertise.
• Well organized, methodical and detail oriented.
• Initiative taker and able to overcome challenges through creativity and innovation.
• Coordinates with colleagues and actively shares expertise; communicates effectively.

Responsibilities

• Physical Design and Timing Closure of complex, low power SoCs for IoT/MCU markets.
• Drive die area, performance, power goals for hierarchical blocks/top.
• Work on floor planning, IO planning, packager co-design, power grid design, P&R, clock tree synthesis, timing closure, IR drop checks, physical verification.
• Deep understanding of SOCs with multiple voltage islands and power-reduction techniques.
• Understand IO planning and package co-design aspects.
• Drive flow/methodology activities to improve QoR.

Skills

Physical design

Timing closure

VLSI design

Scripting languages

Make flow

Team player

Detail oriented

Innovation

Education

Bachelor's or Master's in VLSI design

Tools

Industry standard PD tools

Signoff tools

Place & Route

Clock tree synthesis

Job description

Your Role

Key responsibilities in your new role:

• This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
• Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top.
• Candidate will work on various stages of physical design implementation which includes floor planning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IR drop, physical verification checks.
• Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques.
• Candidate should have good understanding of IO planning, package co-design aspects.
• Candidate is expected to drive flow/methodology activities to improve upon QoR.

Your Profile

Qualifications and skills to help you succeed

• Bachelor's or Master's degree with specialization in VLSI design
• Must have 8+ years of hands‑on experience in physical design and timing closure of SoCs
• Experience of industry standard tools for physical design and signoff
• Experience in scripting languages (shell, perl, tcl) and Make flow
• Understanding of 40nm/28nm/22nm technologies and associated physical design challenges
• Must be a good team player and should have desire to learn and explore
• Strong commitment and determination in area of expertise
• Must be well organized, methodical and detail oriented
• Takes initiatives and overcomes challenges through creativity and innovation
• Coordinates with colleagues and actively shares expertise with others
• Shares information comprehensively and effectively

Contact

[e-mail]

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