STA Engineer 5+ years

HCLTech; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

HCLTech Bengaluru invites an experienced Static Timing Analysis (STA) Engineer to join our VLSI timing signoff team. You will apply STA at subsystem level, analyze setup/hold margins, and work with Physical Design and design teams to ensure timing closure.

We seek a BE/B.Tech with 5+ years of experience, deep knowledge of SDC constraints, CDC, and low-power concepts, and hands-on use of PrimeTime. Share your resume to [e-mail].

Qualifications

• 5+ years of experience in VLSI design and timing signoff.
• Strong expertise in STA and subsystem timing.
• Experience with PrimeTime and timing signoff flows.
• Knowledge of SDC constraints, CDC, and low-power concepts.
• Experience collaborating with Physical Design and Design teams.

Skills

STA

Timing Signoff

PrimeTime

SDC constraints

CDC/Low-power concepts

Debug setup/hold violations

PD/Design collaboration

Education

BE/B.Tech

Tools

PrimeTime

Job description

We are looking for a skilled Static Timing Analysis (STA) Engineer with 5+ years of experience in VLSI design and timing signoff.

Qualification: BE/B.Tech

• Strong expertise in STA and Subsystem level
• Experience with PrimeTime and Timing Signoff flows
• Knowledge of SDC constraints, CDC, and low-power design concepts
• Ability to analyze and debug setup/hold violations
• Experience working with Physical Design and Design teams

Interested candidates kindly share below details & updated resume at [e-mail]