STA Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru seeks a Timing Closure Leader to deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.

You will collaborate with RTL, PD and DFT teams, develop and validate timing constraints, optimize synthesis flows with Fusion Compiler and Design Compiler, and apply AI-driven design techniques to accelerate exploration and reduce cycle time.

Qualifications

• Experience delivering sign-off STA and timing closure leadership.
• Strong collaboration with RTL, PD and DFT teams.
• Experience with synthesis tools and timing constraints.

Responsibilities

• Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.
• Customer Impact: Translate technical excellence into measurable outcomes for customers - faster turnaround, improved QoR, and optimized PPA trade-offs.
• Constraint Development: Architect and validate timing constraints to guarantee design reliability and seamless integration into customer workflows.
• Synthesis & Optimization: Own synthesis flows using Fusion Compiler and Design Compiler, achieving customer-defined targets for timing, area, and power.
• Cross-functional Collaboration: Partner with RTL, PD, and DFT teams to proactively resolve design challenges, ensuring smooth delivery for customer programs.
• AI-driven Design: Apply reinforcement learning tools (DSO.ai) to accelerate design space exploration, delivering innovative solutions that reduce cycle time.
• Low Power & UPF: Implement and verify UPF-based power intent, ensuring energy-efficient designs aligned with customer requirements.
• Formal Equivalence & ECOs: Guarantee functional correctness through formal verification and ECO generation, enabling reliable customer tape-outs.

Skills

Timing closure leadership

Synthesis optimization

Constraint development

Cross-functional collaboration

AI-enabled design

Tools

Fusion Compiler

Design Compiler

DSO.ai

Job description

Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.

Responsibilities

• Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.
• Customer Impact: Translate technical excellence into measurable outcomes for customers - faster turnaround, improved QoR, and optimized PPA trade-offs.
• Constraint Development: Architect and validate timing constraints to guarantee design reliability and seamless integration into customer workflows.
• Synthesis & Optimization: Own synthesis flows using Fusion Compiler and Design Compiler, achieving customer-defined targets for timing, area, and power.
• Cross-functional Collaboration: Partner with RTL, PD, and DFT teams to proactively resolve design challenges, ensuring smooth delivery for customer programs.
• AI-driven Design: Apply reinforcement learning tools (DSO.ai) to accelerate design space exploration, delivering innovative solutions that reduce cycle time.
• Low Power & UPF: Implement and verify UPF-based power intent, ensuring energy-efficient designs aligned with customer requirements.
• Formal Equivalence & ECOs: Guarantee functional correctness through formal verification and ECO generation, enabling reliable customer tape-outs.