SRAM Design Engineer

MediaTek; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

MediaTek Bengaluru is seeking an SRAM Design Engineer to participate in designing Fast Cache SRAM blocks for xPU systems, working closely with CPU/GPU/APU teams. The role emphasizes timing, power, and area optimization with strong verification and collaboration across design and layout groups.

The candidate should have hands-on experience in schematic capture, simulations, and post-layout checks, with proficiency in Verilog/SystemVerilog and scripting in Python or Perl.

Qualifications

• Experience in designing SRAM for xPU systems and memory subsystems.
• Proficiency in Verilog/SystemVerilog and post-layout verification.
• Strong scripting skills (Python/Perl) and willingness to collaborate with multiple teams.

Responsibilities

• Design FCI SRAM blocks for xPU systems with SRAM team.
• Define design specs with CPU/GPU/APU teams.
• Optimize SRAM for power, timing, area, and yield; implement single and two-port SRAM circuits.
• Perform schematic capture, simulations, and margin checks; verify post-layout timing and power.
• Collaborate with layout and post-silicon debugging teams; validate SRAM designs (EM/IR, Power On).

Skills

Python

Verilog

SystemVerilog

Schematic capture

Tools

XA

AFS-Mega

HSPICE

NANOTIME

Virtuoso

Custom Compiler

XA-RA

Totem

Job description

• Design FCI (Fast Cache instances) for xPU (CPU/GPU) systems with the SRAM team.
• Define design specs with CPU/GPU/APU teams.
• Optimize SRAM for power, timing, area, and yield.

Job Description

• Design FCI (Fast Cache instances) for xPU (CPU/GPU) systems with the SRAM team.
• Define design specs with CPU/GPU/APU teams.
• Optimize SRAM for power, timing, area, and yield.
• Implement Single Port & Two Port SRAM circuits.

Main Requirements and Qualifications

• Design FCI (Fast Cache instances) for xPU (CPU/GPU) systems with the SRAM team.
• Define design specs with CPU/GPU/APU teams.
• Optimize SRAM for power, timing, area, and yield.
• Implement Single Port & Two Port SRAM circuits.
• Perform schematic capture, simulations, and margin checks.
• Measure timing, power, leakage, and optimize post-layout.
• Collaborate with the layout team.
• Validate SRAM designs (EM/IR, Power On, Lockup, etc.).
• Support post-silicon efforts and debugging.
• Preferred Proficiency in Python or Perl, Verilog, System Verilog.
• o Tools:
• XA, AFS-Mega, HSPICE, NANOTIME, Virtuoso, Custom Compiler, XA-RA, Totem