Memory Circuit Design Engineer

Clarus Advisers; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Clarus Advisers in Bengaluru, India, seeks an experienced SRAM design engineer to lead transistor-level SRAM design, layout supervision, and verification for advanced FinFET processes.

The role includes developing Python-based automation for SRAM compiler workflows, optimizing power, performance, and area, and collaborating with SoC and product teams.

Qualifications

• Btech, Mtech or PhD preferred.
• 5+ years SRAM design experience on FinFET processes.
• Experience with single-port, dual-port SRAM macros and sense-amplifiers.
• Python scripting to parse data and automate tasks.
• Proven track record of delivering designs to production.

Responsibilities

• Embedded SRAM design: transistor-level circuit design, supervising layout verification and debugging of SRAM macros.
• SRAM compiler development: automate assembly and validation of multiple unique SRAM macros using NVIDIA's compute resources.
• Explore future process nodes and develop techniques to optimize power, performance, and area.

Skills

SRAM design

Python scripting

Education

BTech/MTech/PhD preferred

Job description

Company Overview

Our client is a Research lead organisation focusing on cutting-edge software, AI, and hardware innovation.

Position Overview

This position focuses on SRAM circuit design and compiler development for advanced semiconductor technologies. The role involves transistor-level SRAM design, layout supervision, physical and logical verification, and debugging of SRAM macros. It also includes developing Python-based automation for SRAM compiler workflows, optimizing designs for power, performance, and area across advanced process nodes, and collaborating with SoC, silicon validation, and product teams.

Responsibilities

• Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.


• SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.


• Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.

Skills & Experience

• Btech, Mtech or PhD preferred


• 5+ years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes


• Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers


• Python scripting ability to parse data and automate tasks


• Successful track record of delivering designs to production