NPU/AI Processor Synthesis -Staff Engineer

Qualcomm; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Qualcomm in Bengaluru is seeking an experienced NPU Synthesis Lead to drive synthesis and timing closure for Neural Processing Unit (NPU) IP. This role requires collaboration with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.

The ideal candidate has 15+ years of experience in ASIC synthesis, with strong proficiency in industry-standard synthesis tools like Design Compiler and Genus. A Bachelor's/Master's in Electrical Engineering or a related field is required.

Qualifications

• 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.
• Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.

Responsibilities

• Lead RTL-to-gate-level synthesis for NPU IP and subsystems.
• Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
• Collaborate with STA teams to resolve setup/hold violations.

Skills

ASIC design flow

Synthesis tools (Design Compiler, Genus)

STA tools (PrimeTime)

Automation (Tcl, Perl, Python)

Collaboration with cross-functional teams

Low power strategies

Education

Bachelor's/Master's in Electrical Engineering

PhD in relevant fields

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime

Job description

Role Overview

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting‑edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high‑quality netlists for advanced technology nodes.

Key Responsibilities

• Lead RTL‑to‑gate‑level synthesis for NPU IP and subsystems using industry‑standard tools (Synopsys Design Compiler, Cadence Genus).
• Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
• Drive pre‑layout and post‑layout timing closure across multiple voltage and process corners.
• Collaborate with STA teams to resolve setup/hold violations.
• Apply physical‑aware synthesis techniques to meet aggressive PPA targets.
• Implement low‑power strategies using UPF/CPF flows.
• Validate and maintain SDC constraints for clocks, I/O delays, multi‑cycle paths, and false paths.
• Work closely with RTL design, DFT, and physical design teams for seamless handoff.
• Provide feedback to architecture and RTL teams for QoR improvements.
• Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.
• Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.
• Lead synthesis teams and drive best practices across synthesis and timing teams.

Required Skills

• Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.
• Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).
• Experience with UPF/CPF‑based flows and multi‑voltage designs.
• Advanced skills in Tcl, Perl, Python for automation.
• Familiarity with Spyglass, Lint, CDC tools, and power analysis tools.
• Ability to lead synthesis teams and coordinate with cross‑functional groups.
• Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.
• 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.
• Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical‑aware flows.
• Prior tape‑out experience for NPU or DSP cores.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and at least 4 years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, and at least 3 years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, and at least 2 years of Hardware Engineering or related work experience.

Qualcomm is an equal‑opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number.

Qualcomm expects its employees to abide by all applicable policies and procedures, including security and other requirements regarding protection of company confidential information, to the extent permissible under applicable law.

If you would like more information about this role, please contact Qualcomm Careers.