NPU/AI Processor Synthesis - Principal Engineer/Manager

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Qualcomm is seeking an NPU Synthesis Lead in Bengaluru, India. This role is pivotal in driving synthesis and timing closure for Neural Processing Unit (NPU) IP in cutting-edge SoCs. The ideal candidate will lead synthesis processes and ensure high-quality netlists by collaborating with various engineering teams.

Key qualifications include a Bachelor's or Master's in Electrical Engineering and substantial experience in ASIC synthesis. The position also entails mentoring junior engineers and exploring innovative methodologies.

Qualifications

• Bachelor’s degree in Computer Science or related field and 6+ years of experience.
• Master’s degree with 5+ years of experience or PhD with 4+ years.
• 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI design.

Responsibilities

• Lead RTL-to-gate-level synthesis for NPU IP.
• Drive pre-layout and post-layout timing closure.
• Optimize for performance, power, and area targets.
• Collaborate with multiple teams for effective design flow.

Skills

Strong knowledge of ASIC design flow

Proficiency in synthesis tools (Design Compiler, Genus)

Advanced skills in Tcl, Perl, Python

Experience with UPF/CPF-based flows

Ability to lead synthesis teams

Education

Bachelor's/Master's in Electrical Engineering, Computer Engineering

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime

Job description

Role Overview

The NPU Synthesis Lead will be responsible for driving synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting‑edge SoCs. This role involves leading synthesis flows, optimizing for PPA (Performance, Power, Area), and collaborating with architecture, RTL, and physical design teams to ensure high-quality netlists for advanced technology nodes.

Key Responsibilities

• Synthesis Ownership
  • Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).
  • Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
• Timing Closure
  • Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
  • Collaborate with STA teams to resolve setup/hold violations.
• Power & Area Optimization
  • Apply physical-aware synthesis techniques to meet aggressive PPA targets.
  • Implement low-power strategies using UPF/CPF flows.
• Constraint Management
  • Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.
• Cross-Functional Collaboration
  • Work closely with RTL design, DFT, and physical design teams for seamless handoff.
  • Provide feedback to architecture and RTL teams for QoR improvements.
• Quality Checks
  • Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.
• Flow Innovation
  • Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.
• Team Leadership
  • Mentor junior engineers and drive best practices across synthesis and timing teams.

Minimum Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
• Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Required Skills

• Technical Expertise
  • Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.
  • Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).
• Low-Power Design
  • Experience with UPF/CPF-based flows and multi-voltage designs.
• Scripting
  • Advanced skills in Tcl, Perl, Python for automation.
• EDA Tools
  • Familiarity with Spyglass, Lint, CDC tools, and power analysis tools.
• Leadership
  • Ability to lead synthesis teams and coordinate with cross-functional groups.
• Education
  • Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.
• Experience
  • 15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.
• Preferred
  • Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.
  • Prior tape-out experience for NPU or DSP cores.

Equal Opportunity & Disability Accommodations

Qualcomm is an equal opportunity employer. If you are an individual with a disability, we are committed to providing an accessible process and reasonable accommodations. For accommodations, contact [e-mail].