DFT Engineer - Mumbai

N Human Resources & Management Systems; Mumbai; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

N Human Resources & Management Systems in Mumbai is hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key responsibilities include scan insertion, ATPG pattern generation, MBIST/LBIST architecture, boundary scan, and test point insertion.

Qualifications

• 5+ years hands-on DFT experience (ATPG, scan, MBIST/LBIST).
• Strong knowledge of test coverage and silicon debug.

Responsibilities

• Own DFT architecture and implementation across blocks.
• Perform scan insertion, ATPG, and fault coverage analysis.
• Define MBIST/LBIST architectures for memory/logic.
• Develop boundary scan and DFT constraints.
• Lead and mentor a team of 3-4 engineers.
• Collaborate with RTL, Physical Design, and STA teams.

Skills

ATPG/Scan

MBIST/LBIST

DFT Architecture

JTAG/IEEE 1149.1

Test Pattern Gen

Silicon Debug

Team Leadership

Tools

Tessent

DFTMAX

Job description

N Human Resources & Management Systems | Full time

We are hiring a DFT Engineer to join our VLSI delivery team. You will own design-for-test architecture and implementation across design blocks, ensuring strong fault coverage and manufacturing test readiness from RTL through tapeout.

Key Responsibilities:

• Scan insertion, ATPG pattern generation, and fault coverage analysis
• MBIST/LBIST architecture definition and implementation for memory and logic test
• Boundary scan (JTAG/IEEE 1149.1) and DFT-aware constraint development
• Scan chain stitching, compression, and test point insertion
• Debug of silicon test failures and correlation with simulation results
• Lead and mentor a team of 3-4 engineers on DFT methodology and flows
• Partner closely with RTL design, Physical Design, and STA teams on testability closure

Requirements:

• 5+ years of hands-on experience in DFT (ATPG, scan, MBIST/LBIST)
• Strong knowledge of Tessent/DFTMAX or similar industry-standard DFT tools
• Comprehensive understanding of test coverage, pattern generation, and silicon debug