Sr Engineer & Technical Lead-DFT

Cyient; Hyderabad, Bengaluru; Hybrid; INR 1,200,000 - 1,700,000; Full time

Job summary

Cyient Semiconductor is seeking a Senior DFT Engineer to lead DFT implementations for complex SoCs. The role requires hands-on experience with Mentor Tessent tools, including scan insertion, ATPG, and diagnosis, to drive test coverage closure.

The candidate will collaborate with design, verification, and physical design teams, perform DRC checks, and support silicon bring-up and production ramp. Immediate joining preferred for 0-30 days.

Qualifications

• 4-12 years of experience in DFT Engineering.
• Hands-on expertise in Mentor Tessent DFT Tools: Tessent Scan, Tessent ATPG, Tessent Diagnosis, Tessent Compression, Tessent EDT.
• Strong understanding of scan architecture, insertion, ATPG, fault modelling, fault simulation, test coverage analysis, and DFT DRC.

Responsibilities

• Develop and implement DFT architecture for complex SoCs and IPs.
• Perform Scan Insertion, Scan Compression and ATPG using Mentor Tessent Tool Suite.
• Generate and debug stuck-at, transition, bridge and path delay fault patterns.
• Drive DFT implementation and test coverage closure activities.
• Work closely with Design, Verification, Physical Design and Product Engineering teams.
• Perform DRC analysis and resolve DFT-related issues.
• Execute diagnosis and failure analysis for silicon bring-up support.
• Validate test patterns on ATE platforms and support production ramp.
• Create and review DFT RTL, test plans, methodologies and sign-off reports.
• Ensure high-quality DFT implementation while meeting project schedules.

Skills

DFT Engineering

Mentor Tessent DFT Tools

Scan Architecture

ATPG

Fault Modelling

Fault Simulation

Test Coverage Analysis

DFT DRC

Debugging

Education

B.E./B.Tech or M.E./M.Tech in Electronics or ECE

Tools

Mentor Tessent Scan

Tessent ATPG

Tessent Diagnosis

Tessent Compression

Tessent EDT

Job description

Job Description: Senior DFT Engineer & Lead

Location: Bangalore / Hyderabad
Experience: 4-12 Years
Employment Type: Full Time
Joining Requirement: Immediate Joiners Only (0-30 Days Preferred)

About the Role

Cyient Semiconductor is looking for highly skilled and motivated Senior DFT Engineers with strong expertise in Mentor Tessent DFT solutions to join our growing semiconductor engineering team. The ideal candidate should have hands-on experience in DFT implementation, scan insertion, ATPG, diagnosis, and test coverage closure for complex SoCs.

Key Responsibilities

• Develop and implement DFT architecture for complex SoCs and IPs.
• Perform Scan Insertion, Scan Compression and ATPG using Mentor Tessent Tool Suite.
• Generate and debug stuck-at, transition, bridge and path delay fault patterns.
• Drive DFT implementation and test coverage closure activities.
• Work closely with Design, Verification, Physical Design and Product Engineering teams.
• Perform DRC analysis and resolve DFT-related issues.
• Execute diagnosis and failure analysis for silicon bring-up support.
• Validate test patterns on ATE platforms and support production ramp.
• Create and review DFT RTL, test plans, methodologies and sign-off reports.
• Ensure high-quality DFT implementation while meeting project schedules.

Required Skills

Mandatory Skills

• 4-12 years of experience in DFT Engineering.
• Strong hands-on expertise in Mentor Tessent DFT Tools: Tessent Scan, Tessent ATPG, Tessent Diagnosis, Tessent Compression, Tessent EDT.
• Strong understanding of: Scan Architecture, Scan Insertion, ATPG, Fault Modelling, Fault Simulation, Test Coverage Analysis, DFT DRC.
• Experience in Scan Compression and Coverage Closure.
• Good understanding of SoC Design Flow.
• Strong debugging and problem-solving skills.

Preferred Skills

• Experience in LBIST / MBIST implementation.
• Experience with IJTAG (IEEE 1687) and Boundary Scan (JTAG).
• Knowledge of RTL Design and Verification.
• Experience in advanced technology nodes.
• Scripting expertise in Tcl, Perl, Python or Shell.

Educational Qualification

• B.E / B.Tech / M.E / M.Tech in Electronics, VLSI, ECE or related disciplines.

Why Join Cyient Semiconductor?

• Opportunity to work on cutting-edge SoC and semiconductor programs.
• Exposure to advanced DFT methodologies and technologies.
• Collaborative environment with industry-leading experts.
• Fast-paced growth and leadership opportunities.