SoC Verification

NXP Semiconductors; Bengaluru; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

NXP Semiconductors in Bengaluru is seeking an experienced SoC verification engineer to design and implement verification environments for complex multi-million gate designs. You will develop test benches, stimulus, and coverage-driven verification across multiple clocks and power domains.

You'll work with RTL, microarchitecture concepts, and industry-standard simulators to debug issues, drive regression, and ensure robust validation of subsystem and SoC designs.

Qualifications

• BTech/MTech with 5-10 years experience in SOC/Subsystem verification of complex multi-million gate designs with multiple clocks/power domains.
• Hands-on in C and UVM/SV based test environments, Verilog/VHDL, and simulators (Synopsys/Cadence/Mentor).
• Deep understanding of RTL/Gate netlist, coverage driven verification and regression management.

Responsibilities

• Develop verification test benches and components including drivers, monitors and checkers.
• Create constrained-random stimuli and debug failures to root cause.
• Map requirements to a traceable verification plan and analyze coverage results.

Skills

C programming

UVM/SV based test env

Verilog/VHDL

RTL debugging

Coverage-driven verification

Arm cores

Bus protocols AXI/AHB

Microarchitecture understanding

Interconnect/NIC

SoC/subsystem verification

Education

BTech/B.E. in relevant field

MTech in relevant field

Tools

Synopsys tools

Cadence tools

Mentor Graphics tools

Job description

## SoC VerificationApply: Noida: Bangalore: Full time: Posted Today: R-10066969**Job Summary**The Verification role will involve many aspects of functional verification using most effective methodologies in context of Subsystem/SoC/System Level. A strong ability to map requirements into a traceable verification plan is important. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation , debugging failures and creating simulation cases for various scenariosExpectations include:* Verification planning;* Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs* Development of direct and constrained-random stimulus* Understands and analyzes RTL code, functional, assertion coverage results* Understands and develops system Verilog assertions* Strong skills in debug, failure re-creation and root cause analysis* Applicant should have efficient debugging and logic skills**Job Qualifications**BTech/MTech with 5-10 years experience in SOC/Subsystem verification of complex multi-million gate designs with multiple clocks/power domains. Experience in below areas with strong hands on knowledge in below areas is needed* C and UVM/SV based test environment,* HDLs (Verilog/VHDL), simulators (Synopsys/Cadence/Mentor)* Understanding of the design/architecture and ability to debug RTL/Gate netlist* Coverage driven verification , regression management* Microcontroller architecture, ARM Cores, Interconnect(NIC, FlexNoC), Cache Coherency* Bus Protocols like AHB, AXI, ACE* Following skills will have additional value: + Memory controllers (Flash, SRAM,DDR3/4/LPDDR) + Protocols like PCIe, MIPI, GPU (Graphics processing), VPU (Video Processing), Ethernet, USB, Image + Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization + Low Power intent verification using CPF, UPF