SOC/Subsystem Principal Verification Engineer

Cadence; Hyderabad; On-site; INR 4,000,000 - 8,500,000; Full time

Job summary

Cadence Hyderabad is seeking an experienced SOC/Subsystem Lead Verification Engineer to own the verification strategy, planning, execution, and closure for a complex SoC block. You will lead cross-functional teams across design, firmware, emulation, and post-silicon validation to ensure functional correctness and tapeout readiness.

You will develop UVM-based environments, define coverage models, drive test plans for protocol, performance, power, reset, and security, and mentor junior engineers

Qualifications

• 10-20 years of ASIC/SoC verification experience.
• Proven ownership of subsystem or SoC-level verification.
• Strong debugging across RTL, testbench, and system levels.
• Experience leading verification closure for complex designs.
• Experience with cross-functional programs and schedules.

Responsibilities

• Lead verification from architecture review to closure for SoC/subsystem.
• Define verification strategy, architecture, and plan.
• Develop UVM-based environments, testbenches, and assertions.
• Drive coverage closure across code and functional coverage.
• Coordinate with design, firmware, emulation, and post-silicon teams.
• Mentor junior engineers and review verification code.
• Drive signoff readiness and tapeout support.

Skills

SystemVerilog

UVM

Verification planning

Debug RTL

Python scripting

Protocol knowledge (AXI/NoC/PCIe)

Team leadership

Cross-functional collaboration

Tools

Emulation

FPGA prototyping

Scoreboards

Checkers

Job description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

About the Role

A SOC/Subsystem Lead Verification Engineer is responsible for owning the verification strategy, planning, execution, and closure for a complex SoC block or subsystem. The role combines strong hands-on verification depth with technical leadership, cross-functional coordination, and delivery accountability.

Responsibilities

• Lead verification of SoC or subsystem-level designs from architecture review through verification closure, ensuring functional correctness, coverage closure, and high-quality tapeout readiness.
• Drive methodology, team execution, debug, and alignment with design, architecture, firmware, emulation, and system teams.
• Define subsystem or SoC-level verification strategy, architecture, and execution plan.
• Review specifications, architecture documents, and micro-architecture for testability and verification completeness.
• Create and own verification plans, feature mapping, coverage models, and closure criteria.
• Lead development of UVM/SystemVerilog-based verification environments, reusable testbenches, checkers, scoreboards, monitors, and assertions.
• Drive test planning for protocol, performance, power, reset, interrupt, security, coherency, and error scenarios.
• Own regression strategy, triage, debug, and bug tracking to closure.
• Lead coverage closure across code coverage, functional coverage, assertions, and scenario coverage.
• Coordinate with design, DFT, firmware, architecture, emulation, and post-silicon teams.
• Mentor junior engineers and review verification code, test plans, and debug approaches.
• Identify verification gaps, schedule risks, and quality risks early and drive mitigation.
• Support formal verification, emulation, prototyping, and low-power verification where applicable.
• Drive signoff readiness and contribute to tapeout reviews.

Qualifications

• 10-20years of experience in ASIC/SoC verification.
• Strong experience in subsystem or SoC-level verification ownership.
• Proven track record of leading verification closure for complex designs.
• Strong debugging skills across RTL, testbench, protocol, and system-level issues.
• Experience handling technically complex, cross-functional programs with schedule accountability.

Required Skills

• Strong hands-on expertise in SystemVerilog and UVM.
• Solid understanding of verification methodologies, constrained-random testing, assertions, and coverage-driven verification.
• Experience with SoC fabrics and standard protocols such as AXI, AHB, APB, NoC, PCIe, USB, Ethernet, DDR, CXL, CHI, ACE, or similar, depending on domain.
• Experience in subsystem integration verification including resets, clocks, interrupts, boot flows, power states, and register validation.
• Working knowledge of SVA, formal verification concepts, CDC/RDC, and lint flows.
• Familiarity with emulation or FPGA prototyping is strongly preferred.
• Strong scripting skills in Python, Perl, Shell, or Tcl for automation and regression analysis.
• Experience with coverage and debug tools from major EDA vendors.
• Understanding of low-power verification using UPF/CPF is preferred.
• Exposure to firmware-hardware interaction and performance validation is a plus.

Preferred Skills

• Lead a small to mid-sized verification team or act as technical lead for a larger program.
• Break down high-level milestones into execution plans and track delivery.
• Drive technical reviews and decision-making.
• Mentor engineers on methodology, coding quality, and debug efficiency.
• Communicate status, risks, dependencies, and closure metrics clearly to stakeholders.