Principal Engineer – SoC Design Verification

Jobtailor; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Jobtailor is seeking an experienced Verification Lead in Bengaluru, India to define and drive verification strategy for advanced platform products and lead verification across SoCs and subsystems. You will provide technical leadership for verification of Smart Analog and Sensor SoCs, own methodologies, and signoff across environments.

Key responsibilities include shaping test plans, coverage strategies, reusable components, and scalable verification frameworks.

Qualifications

• Minimum BS and 15+ years of relevant industry experience.
• Extensive experience in UVM-based verification.
• Experience verifying complex SoCs.
• Experience building reusable verification environments.
• Experience defining and tracking coverage metrics.
• Preferred: Experience with emulation and prototyping.
• Preferred: Experience with safety and security verification.
• Preferred: Experience with performance verification.
• Preferred: Experience leading globally distributed teams.

Responsibilities

• Define and drive verification strategy for advanced platform products.
• Provide technical leadership for verification of complex Smart Analog & Sensor SoCs.
• Own verification strategy, methodology, planning, execution, and signoff across subsystem and full-chip environments.
• Drive verification quality across processor, accelerator, memory, connectivity, and sensor subsystems.
• Develop chip-level and subsystem-level verification strategies.
• Define test plans, coverage plans, verification methodologies, and signoff criteria.
• Lead verification engineers across internal and external resources.
• Lead verification of interfaces, bus interconnects, DMA engines, memory architectures, security and safety functions, data processing pipelines, peripherals, and application use cases.
• Coordinate subsystem and SoC-level verification activities.
• Develop scalable verification infrastructure and automation.
• Collaborate with architects and designers throughout the development cycle.
• Coordinate with physical design, emulation, and related engineering teams.
• Own verification closure and signoff readiness.
• Lead development of UVM-based verification environments and reusable verification components.
• Drive scalable verification frameworks across multiple SoC programs.
• Drive closure of functional coverage, code coverage, assertions, and safety requirements coverage.
• Define verification KPIs and dashboards.
• Mentor senior verification engineers.
• Lead reviews and verification signoff decisions.
• Drive adoption of advanced verification methodologies.

Skills

UVM-Based Verification

SoC Verification

Verification Strategy Development

Mentoring Verification Engineers

Coverage Metrics Tracking

Education

BS in Electrical/Computer Engineering

Tools

Emulation

Prototyping

Reusable Verification Components

Job description

• Define and drive verification strategy for advanced platform products
• Provide technical leadership for verification of complex Smart Analog & Sensor SoCs
• Own verification strategy, methodology, planning, execution, and signoff across subsystem and full-chip environments
• Drive verification quality across processor, accelerator, memory, connectivity, and sensor subsystems
• Develop chip-level and subsystem-level verification strategies
• Define test plans, coverage plans, verification methodologies, and signoff criteria
• Lead verification engineers across internal and external resources
• Lead verification of interfaces, bus interconnects, DMA engines, memory architectures, security and safety functions, data processing pipelines, peripherals, and application use cases
• Coordinate subsystem and SoC-level verification activities
• Develop scalable verification infrastructure and automation
• Collaborate with architects and designers throughout the development cycle
• Coordinate with physical design, emulation, and related engineering teams
• Own verification closure and signoff readiness
• Lead development of UVM-based verification environments and reusable verification components
• Drive scalable verification frameworks across multiple SoC programs
• Drive closure of functional coverage, code coverage, assertions, and safety requirements coverage
• Define verification KPIs and dashboards
• Mentor senior verification engineers
• Lead reviews and verification signoff decisions
• Drive adoption of advanced verification methodologies

Requirements

• Minimum BS and 15+ years of relevant industry experience
• Extensive experience in UVM-based verification
• Experience verifying complex SoCs
• Experience building reusable verification environments
• Experience defining and tracking coverage metrics
• Preferred: Experience with emulation and prototyping
• Preferred: Experience with safety and security verification
• Preferred: Experience with performance verification
• Preferred: Experience leading globally distributed teams

Core Competencies

Demonstrates expertise in defining and executing verification strategies for complex Smart Analog & Sensor SoCs, with a strong focus on UVM-based verification methodologies and scalable verification infrastructure. Proven ability to lead teams, mentor engineers, and drive verification quality across various subsystems and full-chip environments.

Highest-signal resume keywords

• UVM-Based Verification
• SoC Verification
• Verification Strategy Development
• Mentoring Verification Engineers
• Coverage Metrics Tracking

ATS Optimization Keywords

Hard Skills

• Verification Methodology
• Test Plan Development
• Coverage Plan Definition
• Functional Coverage
• Code Coverage
• Assertions Coverage
• Safety Requirements Coverage
• Data Processing Pipelines
• Memory Architectures
• Interface Verification

Soft Skills

• Technical Leadership
• Collaboration
• Team Coordination
• Mentoring
• Decision-Making

Industry Keywords

• Smart Analog
• Sensor SoCs
• Subsystem Verification
• Safety Verification
• Security Verification

Tools & Technologies

• Verification Infrastructure
• Reusable Verification Components
• Scalable Verification Frameworks
• Emulation
• Prototyping