SoC Physical Design Engineer

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is hiring a Senior Design Engineer for Physical Design to drive ASIC/SoC flows from netlist to GDSII. The role requires hands-on experience with floor planning, timing closure, physical verification, and low-power methodologies.

You will work with RTL, STA, DFT, Library, and CAD teams to meet tape-out deadlines, mentor junior engineers, and optimize PPA across advanced nodes (16nm/7nm/5nm and below). This is a 12-month contract in Hyderabad.

Qualifications

• Experience in ASIC/SoC Physical Design from netlist to GDSII.
• Expertise in floor planning, power planning, placement, CTS, routing, and physical signoff.
• Strong experience in timing closure (setup/hold), MMMC analysis, ECO implementation, and PPA optimization.
• Hands-on experience with physical verification (DRC/LVS), SI, IR drop, and EM/Power integrity analysis.
• Proficient in Tcl, Python, Perl, and Shell scripting for flow automation and productivity enhancements.
• Experience in advanced technology nodes (16nm/7nm/5nm and below) and low-power design methodologies.
• Strong collaboration with RTL, STA, DFT, Library, and CAD teams to deliver successful tape-outs.
• Proven ability to drive block/full-chip closure and mentor junior engineers.

Responsibilities

• Drive block and full-chip physical design closures from RTL to tape-out.
• Collaborate with RTL, STA, DFT, Library, and CAD teams to meet timing, area, and power targets.
• Mentor junior engineers and guide flow automation to improve productivity and signoffs.

Skills

ASIC/SoC Physical Design

Floor planning

Power planning

Placement

Timing closure

Physical verification

Scripting (Tcl/Python/Perl/Shell)

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

PrimeTime

Tempus

Voltus

RedHawk

Calibre

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: Hardware Design Engineer 3

Location: Hyderabad

Duration: 12 Months Contract

Senior Design Engineer Physical Design

• 510+ years of experience in ASIC/SoC Physical Design from netlist to GDSII.
• Expertise in floor planning, power planning, placement, CTS, routing, and physical signoff.
• Strong experience in timing closure (setup/hold), MMMC analysis, ECO implementation, and PPA optimization.
• Hands-on experience with physical verification (DRC/LVS), SI, IR drop, and EM/Power integrity analysis.
• Proficient in EDA tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, and Calibre.
• Skilled in Tcl, Python, Perl, and Shell scripting for flow automation and productivity enhancements.
• Experience in advanced technology nodes (16nm/7nm/5nm and below) and low-power design methodologies.
• Strong collaboration with RTL, STA, DFT, Library, and CAD teams to deliver successful tape-outs.
• Proven ability to drive block/full-chip closure and mentor junior engineers.