Physical Design Engineer

Crintell Technologies LLC.; Bengaluru; On-site; INR 1,800,000 - 4,000,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Bengaluru is seeking a Physical Design Engineer with 6+ years of experience to work on high-performance semiconductor designs.

You will contribute to automated synthesis, timing-driven place-and-route for RTL blocks, clock tree synthesis, floorplanning, IP integration, logic checks, and final sign-off for large IP delivery. Strong scripting and FinFET experience are preferred.

Qualifications

• 6+ years of professional experience in physical design.
• Experience with automated synthesis and timing driven place and route for RTL blocks.
• Experience in clock tree synthesis, power gating, scan stitching, and design optimization for timing/power/area.
• Floor planning, IP integration, and sign-off for large IP delivery.

Skills

Physical design

Timing-driven P&R

Floorplanning

IP integration

Clock tree synthesis

Automation scripting

Design checks

FinFET / Dual Patterning

Problem solving

Communication

Tools

Logic synthesis tools

Place & Route tools

Timing analysis tools

Design checks tools

Schematics/layout tools

Circuit/logic simulation tools

Job description

Urgent Hiring!!!Greetings from Sunrise Biztech Systems Pvt. Ltd.We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.Position: Physical Design EngineerExperience: 6+ yearsLocation: BengaluruContract tenure: 1 yearPREFERRED EXPERIENCE:6 years of professional experience in physical design, preferably with high-performance designs.Experience in automated synthesis and timing driven place and route of RTL blocks for high-speed data path and control logic applications.Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP deliveryStrong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulationVersatility with scripts to automate design flow.Strong communication skills, ability to multi-task across projects, and work with geographically spread out teamsExperience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nmExcellent physical design and timing background.Good understanding of computer organization/architecture is preferred.Strong analytical/problem solving skills and pronounced attention to details