RTL SOC Architect

Mirafra Technologies; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Benefits offered by this job

Design software tools

Job summary

Mirafra Technologies is seeking an accomplished SoC Architect to translate product requirements into scalable micro-architectures and to own top-level integration, clock/reset planning, and power-domain strategies.

You will lead cross-IP coordination with PD, DV, firmware, and software teams, while mentoring engineers and driving delivery of complex SoC programs. Strong RTL, verification, and low-power expertise are required.

Qualifications

• Translate product requirements into scalable micro-architectures.
• Lead top-level SoC integration, clock/reset planning, and cross-IP coordination.
• Expertise in AXI/APB/PCIe and DDR/Ethernet interconnects and peripherals.
• Hands-on CPU/memory subsystem integration (ARM/ARC/RISC-V) and cache/MMU knowledge.
• Deep knowledge of low-power techniques and retention strategies.
• Strong SystemVerilog RTL coding and reusable design practices.
• Ability to guide verification strategy, tests, and regression quality metrics.
• Experience with synthesis, STA, timing closure across PVT corners.
• Familiarity with formal verification and LEC.
• DFT architectures (scan, MBIST, JTAG) and debug infrastructure.
• Post-silicon bring-up, lab debugging, and silicon validation.
• Chip IO planning, pad ring, and packaging constraints.
• Proven mentoring and leadership across SoC programs.
• Embedded hardware/software co-design collaboration.

Responsibilities

• Define and own SoC architecture and power-domain planning.
• Coordinate cross-IP teams and collaborate with firmware/software.
• Review verification plans, sign-off, and quality metrics.
• Lead post-silicon bring-up and validation activities.
• Mentor engineers and drive delivery of complex SoC programs.

Skills

System architecture

SoC integration

Bus protocols

CPU & memory subsystems

Low-power architecture

RTL design

Verification

Synthesis & STA

Formal verification

DFT & debug

Post-silicon bring-up

IO & packaging

Cross-functional leadership

Mentoring

Embedded HW/SW co-design

Education

BTech/ MTech Electrical/Electronics/Computer Science Engineering or Equivalent

Tools

Design Compiler

Job description

• System & Micro-Architecture Definition: Proven ability to translate product requirements and specifications into scalable, power- and performance-optimized micro-architectures.
• SoC Integration & Sub-System Ownership: Extensive experience in top-level SoC integration, clock/reset architecture, power domain planning, and cross-IP coordination.
• Bus Protocols & Interconnects: Strong expertise in industry-standard protocols such as AXI/AHB/APB, coherent interconnects (ACE/CHI preferred), and peripherals including PCIe, USB, Ethernet, CXL, and DDR.
• CPU & Memory Subsystems: Hands-on experience with CPU subsystem integration (ARM/ARC/RISC-V), cache hierarchy, MMU, and memory controller architectures (DDR, LPDDR).
• Low-Power Architecture: Deep understanding of low-power techniques including UPF/CPF, power gating, clock gating, DVFS, multi-voltage designs, and retention strategies.
• RTL Design & Coding Practices: Strong System Verilog RTL coding skills with emphasis on reuse, configurability, and synthesis-friendly design.
• Verification & Quality Sign-off: Ability to review and guide verification strategy, static checks test plans, functional coverage, assertions, and regression quality metrics.
• Synthesis, STA & Sign-off: Expertise in synthesis (Design Compiler), static timing analysis, timing closure across multiple PVT corners, and ECO handling.
• Formal & Equivalence Checking: Strong experience with formal verification and logical equivalence checking (LEC).
• DFT & Debug: Good working knowledge of DFT architectures (scan, MBIST, JTAG) and debug/trace infrastructures.
• Post-Silicon Bring-up: Experience with silicon bring-up, lab debugging, silicon validation, and correlation between RTL, simulation, and silicon behaviour.
• Chip IO & Packaging: Understanding of chip IO planning, pad ring integration, signal integrity considerations, and packaging constraints.
• Cross-Functional Leadership: Ability to work closely with PD, DV, DFT, firmware, and software teams to ensure seamless execution and delivery.
• Mentoring & Technical Leadership: Proven capability to mentor engineers, review designs, drive best practices, and own delivery of complex SoC programs.
• Embedded hardware and software co-design: Collaborate with embedded software and firmware teams to ensure hardware and software co-design, enabling efficient SoC architecture.

Education.

• BTech/ MTech Electrical/Electronics/Computer Science Engineering or Equivalent.