SoC Design Director

Astera Labs; Bengaluru; Vor Ort; INR 1.200.000 - 2.000.000; Vollzeit

Zusammenfassung

Astera Labs in Bengaluru is seeking a Digital Design professional with deep expertise in high-performance controller design. You'll play a crucial role in developing cutting-edge connectivity solutions, focusing on RTL implementation and integration.

The ideal candidate will have 15+ years of experience in digital design, specifically in processor and peripheral implementations. This position offers the opportunity to work with advanced semiconductor technologies and contribute to innovative AI infrastructure solutions.

Qualifikationen

• Minimum 15+ years of digital design experience focused on processor/peripherals.
• Proven expertise in RTL development, synthesis, and timing closure.
• Strong proficiency in SystemVerilog/Verilog and scripting.

Aufgaben

• Design and implement high-performance digital solutions with RTL development.
• Collaborate on IP integration for processor IPs and peripherals.
• Ensure timing closure and oversee pre- and post-silicon debug.

Kenntnisse

RTL development

Micro-architecture development

SystemVerilog/Verilog

PCIe

Scripting (Python/Perl)

Digital design experience

Ausbildung

Bachelor’s in Electronics/Electrical engineering

Master's preferred

Tools

Synopsys/Cadence tools

UVM-based verification

Jobbeschreibung

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for processor IPs and peripherals.
• Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind.
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
• Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows.

Basic Qualifications / Experience Level

• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
• Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise

• Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes (≤ 16nm).
• Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles.
• Hands‑on experience with processor IP (ARM/ARC).
• Experience of working on PCIe (must).
• Hands‑on pre‑silicon and post‑silicon implementation of peripherals for I2C/SPI/UART.
• Hands‑on experience with complex DMA engines and firmware interaction.
• Strong proficiency in SystemVerilog/Verilog and scripting (Python/Perl).
• Silicon bring‑up and post‑silicon debug experience.
• Familiarity with industry standard simulation, debug, quality checking and synthesis tools (Synopsys/Cadence) and UVM-based verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer‑focused attitude.

Preferred Experience

• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation.
• Knowledge of system-level design with ARM/ARC/RISC‑V processor sub‑systems.
• Experience with PCIe/UAL (big plus).
• Understanding of PAD design, DFT, and floor planning.
• Experience in synthesis and timing closure (big plus).
• Experience with NIC, switch, or storage product development.
• Familiarity with working in design and verification workflows in a CI/CD environment.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities.