SMTS DFT Engineer

Mulya Technologies

Bengaluru

On-site

INR 2,500,000 - 4,500,000

Full time

36 hours ago
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Job summary

Mulya Technologies in Bengaluru seeks a senior RTL/DFT engineer with 11–14 years of experience to contribute to advanced chip design and test flows. You will implement scan chains, MBIST/ATPG, write TCL, and help optimize DRCs, OCC, and pattern retargeting across complex SOC projects.

You will also analyze timing reports, drive automation efforts, and propose improvements to flow and methodologies. Prior experience with flow development and POCs is a plus; strong collaboration across hardware

Qualifications

  • Must have familiarity with RTL and be capable of writing small code snippets.
  • Scan-insertion, MBist, ATPG (at least 2/3) experience.
  • Scripting - TCL is must.
  • Knowledge of DRCs, OCC, hierarchical testing, Wrapper cells, MBist, IEEE1149.1, IEEE1167, pattern retargeting.

Skills

RTL coding
Scan-insertion
MBist
ATPG
TCL scripting
IEEE1149.1/IEEE1167
Pattern retargeting
Hierarchical testing
Timing analysis
Python/Perl

Tools

GNU-Make
Python
Perl

Job description

Founded in 2023,by Industry veterans HQ in California,US
Company Description

We are looking for exceptional talent and leadership to join , the world's first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Experience - 11-14 years
Skills
Must-Haves
  • Familiarity with RTL and should be capable of writing small code snippets
  • Scan-insertion, MBist, ATPG ( at least 2/3 )
  • Scripting - TCL is must.
  • Knowledge of common concepts like DRCs, OCC, hierarchical testing, Wrapper cells, MBist, IEEE1149.1 , IEEE1167, pattern retargeting
Good to have:
  • Python/Perl/GNU-Make.
  • Analysing timing reports and constraints for DFT modes
Makes you stand out:
  • Experience in contributing to flow and methodology.
  • Demonstrated instances of running ahead with POCs or automating existing processes
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