DFT Architect

Mulya Technologies; India; Hybrid; INR 3,500,000 - 6,500,000; Full time

Job summary

EnCharge AI is seeking a seasoned DFT Architect to lead testing strategies for edge-to-cloud semiconductor solutions. You will define end-to-end DFT architecture for complex SoCs, drive IST/POST methodologies, and coordinate cross-functional teams to ensure high test coverage with minimal area and power impact.

You will oversee scan insertion, ATPG, and MBIST, while guiding post-silicon validation on ATE to quickly identify and fix silicon issues for reliable edge deployments.

Qualifications

• 14–20 years in DFT with leadership or principal role experience.
• Deep MBIST, memory/logic test, and boundary-scan knowledge.
• Experience with FinFET nodes (7nm/5nm) and low-power design.

Responsibilities

• Define end-to-end DFT architecture for complex SoCs.
• Develop IST and POST strategies for edge data centers.
• Oversee scan insertion and ATPG for reliability and area/power balance.
• Lead post-silicon validation on ATE and root-cause failures.
• Collaborate with Design, Physical Design, and Yield teams.

Skills

DFT experience

Leadership

Edge computing

Tools

Synopsys TestMAX

Siemens Tessent

Cadence Modus

Job description

The 10 Hottest Semiconductor Startups Of 2025 (So Far)

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

Location : Bangalore ( Hybrid- 2days office, 3 days-home)

About Company:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

DFT architect -14-20years

Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As the Design for Test (DFT) Architect, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Key Responsibilities

• Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and MBIST.
• Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
• Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and
• Logic BIST.
• Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact.
• Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements

• Experience: 14-20 years in DFT, with at least 2 years in a leadership or principal role.
• Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
• Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (IEEE 1149.1/6).
• Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
• Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.