DFT Architect

EnCharge AI; India; Hybrid; INR 4,000,000 - 6,000,000; Full time

Job summary

EnCharge AI seeks a senior DFT Architect to define and implement end-to-end DFT architectures for edge-to-cloud SoCs. You will lead MBIST strategies, boundary-scan techniques, and integrate IST/POST for reliable edge deployments.

The role requires 14–20 years in DFT with leadership experience and hands-on use of TestMAX, Tessent, and Modus, across 7nm/5nm FinFET processes. Bengaluru location, hybrid work pattern.

Qualifications

• 14–20 years of DFT experience with leadership exposure.
• Proficient with MBIST and boundary scan (IEEE 1149.1/6).
• Strong experience with FinFET 7nm/5nm nodes.

Responsibilities

• Architect end-to-end DFT architecture for complex SoCs (Hierarchical DFT, Scan compression, MBIST).
• Develop IST and POST strategies for chip health in remote edge data centers.
• Oversee scan insertion and ATPG (Stuck-at, Transition, Path Delay).
• Lead cross-functional collaboration with Design, Physical Design, and Yield teams to balance test coverage, area, and power.
• Lead bring-up and debug on ATE to root-cause silicon failures and optimize test time.

Skills

DFT leadership

MBIST expertise

Edge testing

IST/POST testing

Tools

Synopsys TestMAX

Siemens/Mentor Tessent

Cadence Modus

Job description

The 10 Hottest Semiconductor Startups Of 2025 (So Far

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

Location : Bangalore ( Hybrid- 2days office, 3 days-home)

About Company:

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

DFT architect -14-20years

Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As the Design for Test (DFT) Architect, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment.

Key Responsibilities

• Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, and MBIST.
• Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.
• Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and
• Logic BIST.
• Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact.
• Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements

• Experience: 14-20 years in DFT, with at least 2 years in a leadership or principal role.
• Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus).
• Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities and boundary scan (IEEE 1149.1/6).
• Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).
• Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.