Staff DFT Engineer

EnCharge AI; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

EnCharge AI in Bengaluru is seeking a Staff-level DFT Engineer to lead the DFT architecture for next-generation AI accelerators. With 9–10 years of experience, you will define end-to-end DFT processes, manage constraints, and optimize techniques for Edge AI architectures. This role offers the opportunity to work in a high-impact startup environment and collaborate with seasoned industry veterans. Key technical skills include expertise in DFT tools and scripting for automation.

Qualifications

• 9–10 years of hands-on experience in DFT, with at least one full tape-out cycle in a lead or staff capacity.
• Expert-level proficiency with industry-standard DFT tools.
• Deep understanding of DFT-centric STA and high-speed IO testing.

Responsibilities

• Define and implement the complete DFT architecture.
• Manage DFT constraint development and integration with teams.
• Generate high-coverage test patterns and verify through simulations.
• Implement advanced DFT techniques tailored for Edge AI.
• Design and execute hierarchical DFT flows for large-scale AI SOCs.
• Partner with ATE teams for silicon pattern debugging.

Skills

Hands-on experience in DFT

Expert-level proficiency with industry-standard tools

Deep understanding of DFT-centric STA

Interest in Edge AI hardware

Proficiency in Tcl, Python, or Perl

Tools

Siemens Tessent

Synopsys DFTMAX/TetraMAX

Cadence Genus/Modus

Job description

EnCharge AI is a leader in advanced AI hardware and software systems for edge‑to‑cloud computing. EnCharge’s robust and scalable next‑generation in‑memory computing technology provides orders‑of‑magnitude higher compute efficiency and density compared to today’s best‑in‑class solutions. The high‑performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

The Opportunity

We are looking for a high‑energy, Staff‑level DFT Engineer to join our silicon team. In the fast‑paced world of Edge AI, efficiency is everything.

As a "go‑getter" in a startup environment, you’ll have the autonomy to shape the end‑to‑end DFT insertion process for our next‑generation AI accelerators.

Key Responsibilities

• End‑to‑End DFT Strategy: Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.
• Constraint Management: Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.
• ATPG & Simulation: Generate high‑coverage test patterns (Stuck‑at, At‑speed, Transition, Path Delay) and lead the verification of these patterns through timing‑annotated simulations.
• AI‑Specific Optimization: Implement advanced DFT techniques tailored for Edge AI architectures, such as high‑bandwidth memory testing and low‑power test modes.
• Hierarchical DFT: Design and execute hierarchical DFT flows to manage complexity in large‑scale AI SOCs.
• Silicon Bring‑up: Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.

What You Bring

• Experience: 9–10 years of hands‑on experience in DFT, preferably with at least one full tape‑out cycle in a lead or staff capacity.
• The Toolkit: Expert‑level proficiency with industry‑standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).
• Technical Depth: Deep understanding of DFT‑centric STA, power‑aware DFT, and high‑speed IO testing.
• Startup Mindset: Comfortable wearing multiple hats and building the manual instead of waiting for one.
• Edge AI Interest: A genuine interest in how AI hardware differs from general‑purpose CPUs/GPUs.

Why Join Us?

• High Impact: In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.
• Growth: You’ll be working alongside veterans from top‑tier chipmakers, solving problems that haven't been solved yet.
• Ownership: We value "intrapreneurs"—engineers who treat the product like it’s their own.

Technical Skills at a Glance

• Logic Test: Scan Compression, ATPG (Stuck‑at, Transition), EDT
• Memory Test: MBIST (Programmable/Hardened), Repair Algorithms, JTAG, IEEE 1149.1/6, IEEE 1500 (Wrappers)
• Timing: DFT Constraints, SDC management, Post‑layout STA
• Scripting: Expert in Tcl, Python, or Perl for flow automation