Simulation Acceleration Engineer (BB810FT RM 4553)

Source-Right; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Source-Right is seeking a Simulation Acceleration Engineer in Bengaluru to drive speedups for complex SOC DV through Palladium and Zebu platforms. You will profile RTL/TB, optimize accelerated VIPs, and debug large dumps from accelerated runs, using SystemVerilog/UVM and commercial simulators (VCS/Xcelium) and debug tools (Verdi/Verisium).

You will work with AI-enabled regression flows and Python scripting to accelerate regressions and debugging, collaborating with design or verification leads

Qualifications

• 8–10 years of experience in complex SOC DV and debugging.
• Experience with simulation acceleration platforms like Palladium or Zebu.
• Experience with in-block, sub-systems and SOC level verification.
• Solid knowledge of acceleration methodology.
• Experience handling RTL designs and TBs for speed acceleration.
• Expertise debugging with hardware accelerators and large dumps from accelerated runs.
• Familiarity with accelerated VIPs for high-speed protocols.
• Preferred scripting in Python and AI-enabled regression environments for faster debug.
• Collaborate with design/verification leads to ensure complete verification closure.

Skills

Palladium acceleration

Zebu acceleration

acceleration methodology

RTL profiling

TB profiling

accelerated VIPs

large dump debugging

SystemVerilog/UVM

VCS/Xcelium

Verdi/Verisium

AI-enabled regression flows

Python scripting

Tools

Palladium

Zebu

VCS

Xcelium

Verdi

Verisium

Job description

Position: Simulation Acceleration Engineer (BB810FT RM 4553)

Key skills: Palladium or Zebu simulation acceleration, acceleration methodology, RTL/TB profiling for speed improvement, accelerated VIPs, large dump debugging, SystemVerilog/UVM, VCS/Xcelium, and Verdi/Verisium.

Preferred exposure: AXI, AHB, APB, CHI, PCIe Gen6+, USB3+, Gigabit Ethernet, UCIe, memory standards, Python, and AI-enabled regression/debug flows.

Required Qualification

• 8 to 10 years of experience in working with very complex SOC design DV and debug
• Should have experience in simulation acceleration platforms like Palladium or Zebu
• Experience with in Block, Sub-Systems and SOC level verification
• Should possess solid knowledge simulation acceleration methodology
• Should have experience with handling RTL designs and TBs to be profiled for improving acceleration speed
• Should be expert in debugging with hardware accelerators and handle large dumps from the accelerated runs.
• Should be familiar with handling accelerated VIPs for highspeed protocols
• Preferred to have knowledge in scripting language (Python) and ability work with AI enabled environments for faster TAT of regressions as well as in debug
• Work with design and/or verification lead for ensuring verification plan is complete and closure is assured.

Technical Skills

• Should understand of digital design fundamentals and RTL development.
• Proficiency in Verilog, System Verilog and UVM
• Strong understanding with Palladium or Zebu acceleration tools flows
• Experience with commercial simulators (VCS, Xcelium) and debug platforms (Verdi, Verisium)
• Strong understanding of SoC architecture and bus protocols
• Serial protocols like I2C, I2S, UART etc
• ARM bus protocols like APB, AHB, AXI, CHI etc
• Any one of the high-speed protocols like PCI gen6+, USB3+, Gigabit Ethernet, UCIe
• Memory standards- Flash, NVMe, DDRs, LPDDRs (Preferred)

Soft Skills

• Strong analytical and problem-solving skills.
• Excellent debugging capability.
• Ability to work independently and in cross-functional teams.
• Strong ownership and delivery mindset.