MODULE LEAD - Pre/Post Silicon Validation

Happiest Minds Technologies; Bengaluru; In loco; INR 2.800.000 - 4.200.000; Tempo pieno

Descrizione del lavoro

Happiest Minds Technologies in India seeks a Senior Emulation Engineer to validate pre-silicon RTL/SoC designs on Synopsys ZeBu emulation platforms. You will lead emulation bring-up, develop testbenches, and collaborate with firmware teams for early boot validation.

The role requires 5–8 years in ASIC/SoC emulation, strong Verilog/SystemVerilog/UVM skills, and hands-on experience with ZeBu. A proactive problem-solver with scripting abilities is essential.

Competenze

• 5-8 years of ASIC/SoC emulation experience.
• Hands-on with Synopsys ZeBu platforms.
• Strong knowledge of Verilog/SystemVerilog and UVM.
• Experience with AXI/AHB/APB bus protocols.
• Proficient in Python, TCL, or Shell scripting.
• Strong debugging and problem-solving skills.

Mansioni

• Deploy and validate RTL designs on ZeBu emulation platforms.
• Develop and maintain synthesizable testbenches and emulation flows.
• Bring-up SoC/IP, functional validation, and debug.
• Support firmware and software teams for early boot and system validation.
• Analyze failures, debug RTL issues, and drive root-cause resolution.
• Automate emulation and regression flows using scripting languages.

Conoscenze

ASIC/SoC emulation

ZeBu emulation

Verilog/SystemVerilog/UVM

AXI/AHB/APB

Python/TCL/Shell scripting

Debugging & problem-solving

Formazione

Bachelor's or Master's in Electronics/EE/CE

Strumenti

ZeBu platforms

Palladium/Veloce/FPGA prototyping

TCL scripting

Descrizione del lavoro

Senior Emulation Engineer (ZeBu) | 5-8 Years

Location: Bangalore/Pune, India

Job Overview

We are seeking a motivated Senior Emulation Engineer to support pre-silicon validation of next-generation processor and SoC products using Synopsys ZeBu emulation platforms. The role involves emulation bring-up, hardware-software co-validation, debug, and performance optimization of complex SoC designs.

Key Responsibilities

• Deploy and validate RTL designs on Synopsys ZeBu emulation platforms.
• Develop and maintain synthesizable testbenches and emulation flows.
• Perform SoC/IP bring-up, functional validation, and debug.
• Support firmware and software teams for early boot and system validation.
• Analyze failures, debug RTL issues, and drive root-cause resolution.
• Automate emulation and regression flows using scripting languages.

Required Skills

• 5-8 years of experience in ASIC/SoC emulation.
• Hands-on experience with Synopsys ZeBu platforms.
• Strong knowledge of Verilog/SystemVerilog and UVM.
• Experience with SoC architectures and bus protocols such as AXI/AHB/APB.
• Proficiency in Python, TCL, or Shell scripting.
• Strong debugging and problem-solving skills.

Preferred Skills

• Experience with RISCV processor-based SoCs.
• Exposure to firmware bring-up, Linux boot, or hardware-software co-verification.
• Experience with Palladium, Veloce, or FPGA prototyping is a plus.

Education

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.